Contact structure, contact pad layout and structure, mask combination and manufacturing method thereof
A contact structure, contact pad layout and structure, mask combination and manufacturing method thereof is provided in the present invention. Through the connection of tops of at least two contact plugs in the boundary of core region, an integrated contact with larger cross-sectional area is formed in the boundary of core region. Accordingly, the process of forming electronic components on the contact structure in the boundary of core region may be provided with sufficient process window to increase the size of electronic components in the boundary, lower contact resistance, and the electronic component with increased size in the boundary buffer the density difference of circuit patterns between the core region and the peripheral region, thereby improving optical proximity effect and ensuring the uniformity of electronic components on the contact plugs inside the boundary of core region, and avoiding the collapse of electronic components on the contact plug in the boundary.
1. A semiconductor device, comprising:
multiple core components comprising active areas; and
multiple contact plugs in the semiconductor device, wherein the contact plugs comprises first contact plugs and at least one second contact plug, and the at least one second contact plug is in a shape of inverted-U or comb, and a bottom of each of the contact plugs contacts the active area;
a plurality of first capacitors directly contact on the first contact plugs; and
a second capacitor directly contact on the at least one second contact plug;
wherein a topmost surface of the at least one second contact plug is not lower than a topmost surface of the first contact plug.
2. The semiconductor device of claim 1 , further comprising:
multiple word lines, each of the word lines intersects the active areas;
multiple bit lines, wherein an extending direction of the bit lines is perpendicular to an extending direction of the word lines; and
the at least one second contact plug crossing over at least one of the word lines and aligning with the bit lines.
3. The semiconductor device of claim 1 , further comprising an individual contact pads formed on the top of each of the first contact plug and respectively and electrically contacting the corresponding contact plug.
4. The semiconductor device of claim 1 , wherein the at least one second contact plug is an integrated structure, or at least two of the contact plugs are connected together through a contact pad connected above.
5. The semiconductor device of claim 1 , wherein the second capacitor has a first width, the first capacitor has a second width, and the first width is larger than the second width.
6. The semiconductor device of claim 5 , wherein the first width is larger than a half of the second width.