Parallel acceleration method for memristor-based neural network, parallel acceleration processor based on memristor-based neural network and parallel acceleration device based on memristor-based neural network

1. A parallel acceleration method for a memristor-based neural network, wherein the memristor-based neural network comprises a plurality of functional layers sequentially provided, the plurality of functional layers comprise a first functional layer and a second functional layer following the first functional layer, the first functional layer comprises a plurality of first memristor arrays in parallel, the plurality of first memristor arrays are configured to independently execute an operation of the first functional layer in parallel and to output a plurality of results of the operation to the second functional layer, weight parameters of the memristor-based neural network comprise a plurality of weight parameters of the first functional layer, and the plurality of weight parameters of the first functional layer are written into the plurality of first memristor arrays in one-to-one correspondence, respectively, so as to determine conductances of the plurality of first memristor arrays, and

the parallel acceleration method comprises:

splitting an input data received by the first functional layer into a plurality of sub-input data in one-to-one correspondence with the plurality of first memristor arrays; and

independently executing the operation of the first functional layer on the plurality of sub-input data in parallel via the plurality of first memristor arrays, so as to correspondingly generate a plurality of sub-operation results, wherein the plurality of results of the operation comprises the plurality of sub-operation results,

wherein the weight parameters of the memristor-based neural network further comprise a plurality of weight parameters of functional layers other than the first functional layer, and the plurality of weight parameters of the functional layers other than the first functional layer are written into memristor arrays corresponding to the functional layers other than the first functional layer, so as to determine conductances of the memristor arrays corresponding to the functional layers other than the first functional layer.

2. The parallel acceleration method according to claim 1 , further comprising:

concatenating the plurality of sub-operation results to obtain a concatenate result and executing an operation of the second functional layer on the concatenate result via the second functional layer.

3. The parallel acceleration method according to claim 2 , wherein sizes of the plurality of sub-input data are substantially equal to each other.

4. The parallel acceleration method according to claim 1 , wherein sizes of the plurality of sub-input data are substantially equal to each other.

5. The parallel acceleration method according to claim 1 , wherein independently executing the operation of the first functional layer on the plurality of sub-input data in parallel via the plurality of first memristor arrays, so as to correspondingly generate a plurality of sub-operation results, comprises:

providing the plurality of sub-input data received by the first functional layer to the plurality of first memristor arrays respectively; and

executing the operation of the first functional layer on the plurality of sub-input data at least partially in parallel via the plurality of first memristor arrays, so as to correspondingly generate the plurality of sub-operation results, wherein the plurality of results of the operation comprises the plurality of sub-operation results.

6. The parallel acceleration method according to claim 5 , further comprising:

executing an operation of the second functional layer on the plurality of sub-operation results via the second functional layer.

7. The parallel acceleration method according to claim 6 , wherein the plurality of sub-input data are different from each other.

8. The parallel acceleration method according to claim 5 , wherein the plurality of sub-input data are different from each other.

9. The parallel acceleration method according to claim 1 , wherein the memristor-based neural network implements a convolutional neural network.

10. The parallel acceleration method according to claim 9 , wherein the first functional layer is an initial convolution layer of the memristor-based neural network.

11. The parallel acceleration method according to claim 1 , wherein the plurality of functional layers further comprise a third functional layer, and an output of the third functional layer is provided to the first functional layer.

12. The parallel acceleration method according to claim 1 , wherein the weight parameters of the memristor-based neural network are obtained through ex-situ training.

13. A parallel acceleration processor based on a memristor-based neural network, wherein the memristor-based neural network comprises a plurality of functional layers sequentially provided, the plurality of functional layers comprise a first functional layer, the parallel acceleration processor comprises a plurality of memristor array computing units, the plurality of memristor array computing units comprise a plurality of first memristor array computing units, the plurality of first memristor array computing units are configured to independently execute computing on a plurality of sub-input data split from an input data received by the first functional layer corresponding to an operation of the first functional layer in parallel, and

wherein weight parameters of the memristor-based neural network comprise a plurality of weight parameters of the first functional layer, and the plurality of weight parameters of the first functional layer are written into the plurality of first memristor array computing units in one-to-one correspondence, respectively, so as to determine conductances of the plurality of first memristor array computing units, and

wherein the weight parameters of the memristor-based neural network further comprise a plurality of weight parameters of functional layers other than the first functional layer, and the plurality of weight parameters of the functional layers other than the first functional layer are written into memristor array computing units of the plurality of memristor array computing units corresponding to the functional layers other than the first functional layer, so as to determine conductances of the memristor array computing units corresponding to the functional layers other than the first functional layer.

14. A parallel acceleration device based on a memristor-based neural network, comprising:

a parallel acceleration processor based on the memristor-based neural network, wherein the memristor-based neural network comprises a plurality of functional layers sequentially provided, the plurality of functional layers comprise a first functional layer, the parallel acceleration processor comprises a plurality of memristor array computing units, the plurality of memristor array computing units comprise a plurality of first memristor array computing units, the plurality of first memristor array computing units are configured to independently execute computing on a plurality of sub-input data split from an input data received by the first functional layer corresponding to an operation of the first functional layer in parallel; and

an input interface and an output interface which are coupled to the parallel acceleration processor,

wherein the input interface is configured to receive an instruction to control an operation of the parallel acceleration processor, and the output interface is configured to output a plurality of results of the operation of the parallel acceleration processor,

wherein weight parameters of the memristor-based neural network comprise a plurality of weight parameters of the first functional layer, and the plurality of weight parameters of the first functional layer are written into the plurality of first memristor array in one-to-one correspondence, respectively, so as to determine conductances of the plurality of first memristor arrays, and

wherein the weight parameters of the memristor-based neural network further comprise a plurality of weight parameters of functional layers other than the first functional layer, and the plurality of weight parameters of the functional layers other than the first functional layer are written into memristor array computing units of the plurality of memristor array computing units corresponding to the functional layers other than the first functional layer, so as to determine conductances of the memristor array computing units corresponding to the functional layers other than the first functional layer.