Memory device, a memory system having the same and an operating method thereof in which a row address is not separated depending on pages in a byte mode operation

1. An operating method of a memory device, the method comprising:

receiving a row address;

determining whether an operating mode is a byte mode;

counting up an access count value for the row address while ignoring a page bit, when the operating mode is the byte mode;

selecting a target row hammer address, among target row addresses, using access count values for the target row hammer address;

calculating a victim row address corresponding to the target row hammer address; and

performing a target refresh operation on the victim row address.

2. The method of claim 1 , further comprising:

counting up the access count value for the row address when the operating mode is a normal mode.

3. The method of claim 1 , wherein:

the selecting the target row hammer address comprises selecting a target row address having a largest value, among the access count values, as the target row hammer address.

4. The method of claim 1 , wherein:

the selecting the target row hammer address comprises selecting a row address having a highest number, among the target row addresses, as the target row hammer address when all of the access count values are the same.

5. The method of claim 1 , wherein:

the target refresh operation is not performed when each of the access count values is lower than a reference value.

6. The method of claim 1 , further comprising:

detecting a row hammer attack.

7. The method of claim 1 , wherein:

the target refresh operation is performed per unit time period.

8. The method of claim 7 , wherein:

the unit time period is variable.

9. The method of claim 1 , further comprising:

periodically receiving a refresh command; and

performing a normal refresh operation in response to the refresh command.

10. The method of claim 1 , further comprising:

counting a total count value of a received active command, wherein:

the target refresh operation is performed each time the total count value is a multiple of a predetermined value.

11. A memory system, comprising:

at least one memory device; and

a memory controller configured to control the at least one memory device,

wherein:

the at least one memory device detects a row hammer address while not considering a page separation bit of a row address in a byte mode operation such that different pages within the same row are not differentiated, generates a victim address corresponding to the detected row hammer address, and performs a target refresh operation on the victim address.

12. The memory system of claim 11 , wherein:

the at least one memory device comprises:

a row hammer detection circuit configured to receive the row address and to output the row hammer address; and

a target refresh address generator configured to generate a victim row address corresponding to the row hammer address.

13. The memory system of claim 11 , wherein:

the at least one memory device receives a refresh management command from the memory controller.

14. The memory system of claim 11 , wherein:

the at least one memory device comprises:

a normal refresh address generator configured to receive a refresh command from the memory controller and to generate a normal refresh address in response to the normal refresh command; and

a row hammer detector configured to receive the row address and an active command and to generate the row hammer address.

15. The memory system of claim 14 , wherein:

the at least one memory device further comprises a victim row address selector configured to select one of the normal refresh address and the row hammer address as a victim row address.