Monolithic multi-I region diode limiters
A number of diode limiter semiconductor structures are described. The diode limiters can include a hybrid arrangement of diodes with different intrinsic regions, all formed over the same semiconductor substrate. In one example, a diode limiter includes a first diode having a first doped region formed to a first depth into an intrinsic layer of a semiconductor structure, a second diode having a second doped region formed to a second depth into the intrinsic layer of the semiconductor structure, and at least one passive component. The first diode includes a first effective intrinsic region of a first thickness, the second diode includes a second effective intrinsic region of a second thickness. The first thickness is greater than the second thickness. The passive component is over the intrinsic layer and electrically coupled as part of the diode limiter.
1. A diode limiter, comprising:
a first diode comprising a first doped region formed to a first depth into an intrinsic layer of a semiconductor structure such that the first diode comprises a first effective intrinsic region of a first thickness;
a second diode comprising a second doped region formed to a second depth into the intrinsic layer of the semiconductor structure such that the second diode comprises a second effective intrinsic region of a second thickness, the first thickness being greater than the second thickness; and
at least one passive component.
2. The diode limiter of claim 1 , wherein the passive component is electrically coupled to at least one of the first diode or the second diode as part of the diode limiter.
3. The diode limiter of claim 1 , wherein:
a dopant in the first doped region and in the second doped region comprises a P-type dopant; and
the first diode and the second diode comprise PIN diodes.
4. The diode limiter of claim 1 , wherein:
a dopant in the first doped region and in the second doped region comprises an N-type dopant; and
the first diode and the second diode comprise NIP diodes.
5. The diode limiter of claim 1 , further comprising:
a dielectric layer over the intrinsic layer of the semiconductor structure, the dielectric layer comprising a plurality of openings, wherein:
the first doped region is positioned under a first opening among the plurality of openings; and
the second doped region is positioned under a second opening among the plurality of openings.
6. The diode limiter of claim 5 , wherein a first width of the first opening is different than a second width of the second opening.
7. The diode limiter of claim 1 , wherein:
the first diode further comprises a first sidewall; and
the second diode further comprises a second sidewall.
8. The diode limiter of claim 7 , wherein the diode limiter further comprises an insulator between the first sidewall of the first diode and the second sidewall of the second diode.
9. The diode limiter of claim 1 , wherein:
the first diode further comprises a first doped sidewall; and
the second diode further comprises a second doped sidewall.
10. The diode limiter of claim 9 , wherein the diode limiter further comprises an insulator between the first doped sidewall of the first diode and the second doped sidewall of the second diode.
11. The diode limiter of claim 1 , wherein:
the first diode further comprises a first metallic sidewall conductor; and
the second diode further comprises a second metallic sidewall conductor.
12. The diode limiter of claim 11 , wherein the diode limiter further comprises an insulator between the first metallic sidewall of the first diode and the second metallic sidewall of the second diode.
13. The diode limiter of claim 1 , further comprising:
a dielectric layer over the intrinsic layer of the semiconductor structure; and
a backside contact under the semiconductor structure.
14. The diode limiter of claim 1 , wherein:
the first diode further comprises a first metallic sidewall conductor;
the second diode further comprises a second metallic sidewall conductor;
the diode limiter further comprises:
a first backside contact under the first diode;
a second backside contact under the second diode;
a first topside cathode contact for the first diode;
a first topside anode contact for the first diode;
a second topside cathode contact for the second diode; and
a second topside anode contact for the second diode.
15. The diode limiter of claim 1 , wherein:
the first diode further comprises first doped sidewalls and first metallic sidewall conductors;
the second diode further comprises second doped sidewalls and second metallic sidewall conductors;
the diode limiter further comprises:
a first backside contact under the first diode; and
a second backside contact under the second diode;
the first metallic sidewall conductors are electrically coupled to the first backside contact; and
the second metallic sidewall conductors are electrically coupled to the second backside contact.
16. The diode limiter of claim 15 , further comprising:
a first topside cathode contact for the first diode;
a first topside anode contact for the first diode;
a second topside cathode contact for the second diode; and
a second topside anode contact for the second diode.
17. The diode limiter of claim 1 , further comprising a third diode, the third diode comprising a third doped region formed to a third depth into the intrinsic layer of the semiconductor structure such the third diode comprises a third effective intrinsic region of a third thickness, the second thickness being greater than the third thickness.
18. The diode limiter of claim 17 , wherein:
the first diode further comprises sidewalls;
the second diode further comprises sidewalls;
the third diode further comprises sidewalls; and
the diode limiter further comprises an insulator between a sidewall of the first diode and a first sidewall of the second diode and between a second sidewall of the second diode and a sidewall of the third diode.
19. The diode limiter of claim 17 , further comprising:
topside anode contacts for each of the first diode, the second diode, and the third diode; and
topside cathode contacts for each of the first diode, the second diode, and the third diode.
20. The diode limiter of claim 1 , wherein the diode limiter comprises a multistage hybrid diode limiter of at least two stages.