Clock switching device
Provided is a clock switching device including a first latch circuit, a second latch circuit, and a switching circuit. The first latch circuit latches a first selection signal based on triggering of a first clock signal. The second latch circuit latches a second selection signal based on triggering of a second clock signal. A reset terminal of the second latch circuit is coupled to the first latch circuit. The second latch circuit is selectively reset based on an output of the first latch circuit. The switching circuit is coupled to an output terminal of the first latch circuit and an output terminal of the second latch circuit. The switching circuit selects one of the clock signals as an output clock signal of the clock switching device based on the selection signals.
1. A clock switching device comprising:
a first latch circuit configured to latch a first selection signal among a plurality of selection signals for outputting a first latched selection signal among a plurality of latched selection signals based on triggering of a first clock signal among a plurality of clock signals;
a second latch circuit configured to latch a second selection signal among the selection signals for outputting a second latched selection signal among the latched selection signals based on triggering of a second clock signal among the clock signals, wherein a reset terminal of the second latch circuit is coupled to the first latch circuit, and the second latch circuit is selectively reset based on an output of the first latch circuit; and
a switching circuit coupled to an output terminal of the first latch circuit and an output terminal of the second latch circuit, wherein the switching circuit selects one of the clock signals as an output clock signal of the clock switching device based on the latched selection signals,
wherein the first latch circuit comprises:
a first flip-flop having an input terminal configured to receive the first selection signal, wherein a trigger terminal of the first flip-flop receives the first clock signal; and
a second flip-flop having an input terminal coupled to an output terminal of the first flip-flop, wherein a first output terminal of the second flip-flop is coupled to the switching circuit to provide the first latched selection signal among the latched selection signals, a second output terminal of the second flip-flop is coupled to the reset terminal of the second latch circuit to reset the second latch circuit, and a trigger terminal of the second flip-flop receives the first clock signal.
2. The clock switching device according to claim 1 , wherein one of the trigger terminal of the first flip-flop and the trigger terminal of the second flip-flop is a rising-edge trigger terminal, and the other one of the trigger terminal of the first flip-flop and the trigger terminal of the second flip-flop is a falling-edge trigger terminal.
3. The clock switching device according to claim 1 , wherein the trigger terminal of the first flip-flop and the trigger terminal of the second flip-flop are each a rising-edge trigger terminal or a falling-edge trigger terminal.
4. The clock switching device according to claim 1 , wherein the switching circuit comprises:
a first clock gating cell having a control terminal coupled to the first latch circuit to receive the first latched selection signal, wherein an input terminal of the first clock gating cell receives the first clock signal;
a second clock gating cell having a control terminal coupled to the second latch circuit to receive the second latched selection signal, wherein an input terminal of the second clock gating cell receives the second clock signal; and
an OR gate having a first input terminal and a second input terminal respectively coupled to an output terminal of the first clock gating cell and an output terminal of the second clock gating cell, wherein an output terminal of the OR gate outputs the output clock signal of the clock switching device.
5. The clock switching device according to claim 1 , wherein the switching circuit comprises:
a multiplexer having a first input terminal coupled to the output terminal of the first latch circuit, wherein a second input terminal of the multiplexer is coupled to the output terminal of the second latch circuit, and an output terminal of the multiplexer outputs the output clock signal of the clock switching device.
6. The clock switching device according to claim 1 , further comprising:
a third latch circuit configured to latch a third selection signal among the selection signals based on triggering of a third clock signal among the clock signals, wherein an output terminal of the third latch circuit is coupled to the switching circuit, a reset terminal of the third latch circuit is coupled to the first latch circuit, and the third latch circuit is selectively reset based on the output of the first latch circuit.
7. A clock switching device comprising:
a first latch circuit configured to latch a first selection signal among a plurality of selection signals for outputting a first latched selection signal among a plurality of latched selection signals based on triggering of a first clock signal among a plurality of clock signals;
a second latch circuit configured to latch a second selection signal among the selection signals for outputting a second latched selection signal among the latched selection signals based on triggering of a second clock signal among the clock signals, wherein a reset terminal of the second latch circuit is coupled to the first latch circuit, and the second latch circuit is selectively reset based on an output of the first latch circuit; and
a switching circuit coupled to a first output terminal of the first latch circuit and an output terminal of the second latch circuit, wherein the switching circuit selects one of the clock signals as an output clock signal of the clock switching device based on the latched selection signals,
wherein the second latch circuit comprises:
a first flip-flop having an input terminal configured to receive the second selection signal, wherein a trigger terminal of the first flip-flop receives the second clock signal, and a reset terminal of the first flip-flop is coupled to a second output terminal of the first latch circuit different from the first output terminal of the first latch circuit; and
a second flip-flop having an input terminal coupled to an output terminal of the first flip-flop, wherein an output terminal of the second flip-flop is coupled to the switching circuit to provide the second latched selection signal among the latched selection signals, a reset terminal of the second flip-flop is coupled to the second output terminal of the first latch circuit, and a trigger terminal of the second flip-flop receives the second clock signal.
8. The clock switching device according to claim 7 , wherein one of the trigger terminal of the first flip-flop and the trigger terminal of the second flip-flop is a rising-edge trigger terminal, and the other one of the trigger terminal of the first flip-flop and the trigger terminal of the second flip-flop is a falling-edge trigger terminal.
9. The clock switching device according to claim 7 , wherein the trigger terminal of the first flip-flop and the trigger terminal of the second flip-flop are each a rising-edge trigger terminal or a falling-edge trigger terminal.