Semiconductor devices and data storage system including the same
A semiconductor device includes a substrate, a lower stack structure on the substrate and including lower gate electrodes stacked apart from each other, an upper stack structure on the lower stack structure and including upper gate electrodes stacked apart from each other, a lower channel structure penetrating through the lower stack structure and including a lower channel layer, and a lower channel insulating layer on the lower channel layer the lower channel insulating layer surrounding a lower slit, and an upper channel structure penetrating through the upper stack structure and including an upper channel layer and an upper channel insulating layer on the upper channel layer, the upper channel insulating layer surrounding an upper slit. A width of the lower slit is greater than a width of the upper slit, and a thickness of the lower channel insulating layer is greater than a thickness of the upper channel insulating layer.
1. A semiconductor device comprising:
a substrate;
a lower stack structure on the substrate, and including lower gate electrodes stacked apart from each other;
an upper stack structure on the lower stack structure and including upper gate electrodes stacked apart from each other;
a lower channel structure penetrating through the lower stack structure, and including a lower channel layer and a lower channel insulating layer on the lower channel layer, the lower channel insulating layer surrounding a lower slit; and
an upper channel structure penetrating through the upper stack structure and including an upper channel layer and an upper channel insulating layer on the upper channel layer, the upper channel insulating layer surrounding an upper slit,
wherein the lower channel structure includes a first channel structure, a second channel structure on the first channel structure, and a bent structure between the first channel structure and the second channel structure, a bend in the bent structure corresponding to a difference in widths between the first and second channel structures,
a width of a lower portion of the upper channel structure is less than a width of an upper portion of the lower channel structure, and
a maximum width of the lower slit is greater than a maximum width of the upper slit.
2. The semiconductor device of claim 1 , wherein the lower channel insulating layer includes a first lower channel insulating layer inside of the first channel structure, and a second lower channel insulating layer inside of the second channel structure,
the first lower channel insulating layer surrounds a first lower slit of the lower slit, and the second lower channel insulating layer surrounds a second lower slit of the lower slit, and
a width of the first lower slit is greater than a width of the second lower slit.
3. The semiconductor device of claim 2 , wherein a thickness of the second lower channel insulating layer is greater than a thickness of the first lower channel insulating layer.
4. The semiconductor device of claim 2 , wherein the first lower channel insulating layer surrounds a lower portion, an upper portion and a side surface of the first lower slit.
5. The semiconductor device of claim 1 , wherein the upper channel insulating layer includes a first upper channel insulating layer on the upper channel layer, and a second upper channel insulating layer on the first upper channel insulating layer.
6. The semiconductor device of claim 5 , wherein the first upper channel insulating layer includes a different material from the materials included in the second upper channel insulating layer.
7. The semiconductor device of claim 5 , wherein the first upper channel insulating layer includes a same material from the materials of the second upper channel insulating layer.
8. The semiconductor device of claim 1 , wherein a thickness of the upper channel insulating layer is greater than a thickness of the lower channel insulating layer.
9. The semiconductor device of claim 1 , wherein a volume of the lower slit is greater than a volume of the upper slit.
10. The semiconductor device of claim 1 , wherein the lower slit extends from an interior of the first channel structure to an interior of the second channel structure, and connects to the first channel structure and the second channel structure, and is arranged between the first channel structure and the second channel structure.
11. The semiconductor device of claim 1 , wherein a first width of the upper channel structure is greater than a second width of the second channel structure.
12. The semiconductor device of claim 1 , wherein a first width of the upper channel structure is less than a second width of the second channel structure.
13. The semiconductor device of claim 1 , wherein a first width of the upper channel structure is substantially the same as a second width of the second channel structure.
14. The semiconductor device of claim 1 , wherein an upper portion, a lower portion, and a side surface of the upper slit contact the upper channel insulating layer.
15. The semiconductor device of claim 1 , wherein the lower channel structure includes a lower gate dielectric layer between the lower gate electrodes and the lower channel layer, and
the upper channel structure includes an upper gate dielectric layer between the upper gate electrodes and the upper channel layer.
16. A semiconductor device comprising:
a substrate;
a lower stack structure on the substrate and including lower gate electrodes stacked apart from each other;
an upper stack structure on the lower stack structure and including upper gate electrodes stacked apart from each other;
a lower channel structure penetrating through the lower stack structure and including a lower channel layer, and a lower channel insulating layer on the lower channel layer, the lower channel insulating layer surrounding a lower slit; and
an upper channel structure penetrating through the upper stack structure and including an upper channel layer, and an upper channel insulating layer disposed on the upper channel layer, the upper channel insulating layer surrounding an upper slit,
wherein a maximum width of the lower slit is greater than a maximum width of the upper slit, and
wherein a maximum thickness of the upper channel insulating layer is greater than a maximum thickness of the lower channel insulating layer.
17. The semiconductor device of claim 16 , wherein the lower slit includes a first lower slit adjacent to the substrate and a second lower slit spaced apart from the first lower slit in a direction that is perpendicular to an upper surface of the substrate, and
a width of the first lower slit is greater than a width of the second lower slit.
18. The semiconductor device of claim 16 , wherein the lower slit includes at least one bent portion having a bend associated with a difference in widths between an upper portion of the lower slit and a lower portion of the lower slit.
19. A data storage system comprising:
a semiconductor storage device including a base substrate; active or passive circuits on the base substrate; a substrate on the active or passive circuits; a lower stack structure on the substrate and including lower gate electrodes stacked apart from each other; an upper stack structure on the lower stack structure and including upper gate electrodes stacked apart from each other; a lower channel structure penetrating through the lower stack structure and including a lower channel layer and a lower channel insulating layer on the lower channel layer, the lower channel insulating layer surrounding a lower slit; and an upper channel structure penetrating through the upper stack structure and including an upper channel layer and an upper channel insulating layer disposed on the upper channel layer, the upper channel insulating layer surrounding an upper slit, the semiconductor storage device including an input/output pad electrically connected to the at least one of the active or passive circuits; and
a controller circuitry electrically connected to the semiconductor storage device through the input/output pad and configured to control the semiconductor storage device,
wherein a maximum width of the lower slit is greater than a maximum width of the upper slit, and
a thickness of the upper channel insulating layer is greater than a thickness of the lower channel insulating layer.
20. The data storage system of claim 19 , wherein the lower channel structure includes a first channel structure, a second channel structure on the first channel structure, and a bent portion between the first channel structure and the second channel structure, the bent portion including a bend associated with a difference in widths between the first and second channel structures.