Semiconductor structure and forming method therefor, and memory and forming method therefor

1. A method for forming a semiconductor structure, comprising:

providing a substrate, wherein a sacrificial layer and an active layer on the sacrificial layer are formed on the substrate;

etching the active layer and the sacrificial layer to form active lines along a first direction;

forming a first isolation layer that fills spacing between the active lines;

etching end portions of the active lines to form openings exposing the sacrificial layer;

removing the sacrificial layer along the openings, and forming gaps between a bottom of the active lines and the substrate;

filling the gaps with a conductive material to form bit lines extending along the first direction;

patterning the active lines to form a plurality of active columns that are discrete, the plurality of active columns being arranged in an array along the first direction and a second direction; and

forming a first doped region, a channel region, and a second doped region that are located on a bottom of an active column and sequentially arranged upwards, and forming a gate structure surrounding the channel region;

wherein a method for forming the first doped region comprises: forming a transitional layer with doping elements on the substrate between adjacent active lines or active columns, after the active lines or active columns are formed; and through diffusion treatment, diffusing at least part of the doping elements in the transitional layer into the active line or the active column to form the first doped region.

2. The method for forming a semiconductor structure according to claim 1 , further comprising: filling the openings with the conductive material to form bit line connecting lines located in the openings, wherein a bottom of the bit line connecting lines is connected to the bit lines.

3. The method for forming a semiconductor structure according to claim 2 , wherein the bit line connecting lines and the bit lines are formed in a same processing step.

4. The method for forming a semiconductor structure according to claim 1 , wherein a method for forming the first doped region comprises: performing ion implantation to the active column to form the first doped region located at the bottom of the active column.

5. The method for forming a semiconductor structure according to claim 1 , wherein a method for forming the first doped region, the channel region, and the second doped region comprises: using an in-situ doping process, in the process of forming the active layer, doping the active layer to sequentially form a first doped layer, a channel doped layer, and a second doped layer; and after patterning the active layer to form the active column, the first doped layer, the channel doped layer, and the second doped layer are respectively patterned into the first doped region, the channel region, and the second doped region.

6. The method for forming a semiconductor structure according to claim 1 , wherein a method for forming the gate structure comprises: etching back the first isolation layer to expose a part of the height of the active column; sequentially forming a gate dielectric layer and a gate electrode layer on the first isolation layer of having been etched back and on the exposed active column; and patterning the gate dielectric layer and the gate electrode layer to form the gate structure surrounding the channel region of the active column and expose a top area of the active column.

7. The method for forming a semiconductor structure according to claim 6 , wherein the gate structures on the plurality of active columns arranged on a same straight line along the second direction are connected.

8. The method for forming a semiconductor structure according to claim 6 , wherein after the gate structure is formed, ion implantation is performed on the top area of the active columns to form the second doped region.

9. The method for forming a semiconductor structure according to claim 1 , wherein a plurality of openings are formed at two ends of the plurality of active lines, and the plurality of openings correspond to the active lines on a one-to-one basis, and the openings at ends of a same side of the active lines are distributed at intervals.