Memory device containing magnetic tunnel junction
View Patent ↗Disclosed is a memory device including a lower electrode, a seed layer, a synthetic antiferromagnetic layer, a magnetic tunnel junction, and an upper electrode laminated on a substrate, wherein the magnetic tunnel junction includes a pinned layer, a tunnel barrier layer, and free layers, wherein the free layers include a first free layer, a spacer layer, a coupling layer, a buffer layer, and a second free layer laminated in sequential order.
1. A memory device, comprising a lower electrode, a seed layer, a synthetic antiferromagnetic (SyAF) layer, a magnetic tunnel junction, and an upper electrode laminated on a substrate,
wherein the magnetic tunnel junction comprises a pinned layer, a tunnel barrier layer, and free layers,
wherein the free layers comprise a first free layer, a spacer layer, a coupling layer, a buffer layer, and a second free layer laminated in sequential order, and
wherein the first free layer has a multilayer structure in which an Fe layer and a CoFeB layer are laminated.
2. The memory device according to claim 1 , wherein the coupling layer comprises a material having an HCP structure.
3. The memory device according to claim 2 , wherein the material having an HCP structure comprises cobalt (Co).
4. The memory device according to claim 1 , wherein the buffer layer comprises a material that allows the second free layer to grow in an FCC direction.
5. The memory device according to claim 1 , wherein the buffer layer comprises at least one of platinum (Pt), titanium (Ti), palladium (Pd), magnesium (Mg), cobalt (Co), aluminum (Al), and tungsten (W).
6. A memory device, comprising a lower electrode, a seed layer, a synthetic antiferromagnetic (SyAF) layer, a magnetic tunnel junction, and an upper electrode laminated on a substrate,
wherein the magnetic tunnel junction comprises a pinned layer, a tunnel barrier layer, and free layers,
wherein the free layers comprise a first free layer, a spacer layer, a coupling layer, a buffer layer, and a second free layer laminated in sequential order, and
wherein the second free layer has a multilayer structure in which a Co layer and a Pt layer are alternately laminated two or more times.
7. The memory device according to claim 6 , wherein, in the second free layer having the multilayer structure in which the Co layer and the Pt layer are laminated two or more times, the number of layers of the multilayer structure is 3 to 9.
8. The memory device according to claim 6 , wherein the Co layer of the second free layer has a thickness of 0.2 nm to 0.6 nm.
9. The memory device according to claim 6 , wherein the Pt layer of the second free layer has a thickness of 0.2 nm to 0.6 nm.
10. The memory device according to claim 1 , wherein the coupling layer has a thickness of 0.1 nm to 0.6 nm.
11. The memory device according to claim 1 , wherein the buffer layer has a thickness of 1.0 nm to 3.0 nm.
12. The memory device according to claim 1 , wherein the spacer layer has a thickness of 0.3 nm to 0.8 nm.
13. The memory device according to claim 1 , wherein the lower electrode has a laminated structure in which a first lower electrode comprising tungsten (W) and a second lower electrode comprising titanium nitride (TiN) are laminated.
14. The memory device according to claim 1 , further comprising a bridge layer between the synthetic antiferromagnetic layer and the magnetic tunnel junction.
15. The memory device according to claim 1 , further comprising a capping layer between the magnetic tunnel junction and the upper electrode.