Real-time context specific task manager for multi-core communication and control system
A task manager tightly coupled to a programmable real-time unit (PRU), the task manager configured to: detect a first event; assert, a request to the PRU during a first clock cycle that the PRU perform a second task; receive an acknowledgement of the request from the PRU during the first clock cycle; save a first address in a memory during the first clock cycle of the PRU, the first address corresponding to a first task of the PRU, the first address present in a current program counter of the PRU; load a second address of the memory into a second program counter during the first clock cycle, the second address corresponding to the second task; and load, during a second clock cycle, the second address into the current program counter, wherein the second clock cycle immediately follows the first clock cycle.
1. An integrated circuit comprising:
a processor core that includes a set of program counters;
a task manager circuit coupled to the processor core; and
a spinlock circuit coupled to the task manager circuit, wherein:
the processor core is configured to:
execute a first task; and
based on a first indication from the spinlock circuit that a resource associated with the first task is not available, interrupt execution of the first task to perform a second task using a first program counter of the set of program counters; and
the task manager circuit is configured to:
receive a second indication from the spinlock circuit that the resource is available; and
based on the second indication, cause the processor core to resume the first task by:
causing an address associated with the first task to be loaded into a second program counter of the set of program counters; and
causing the processor core to switch from using the first program counter to using the second program counter.
2. The integrated circuit of claim 1 , wherein:
the address is a first address:
the integrated circuit further comprises a memory coupled to the task manager circuit; and
the task manager circuit is configured to, based on the second indication, cause a second address stored in the first program counter to be stored in the memory.
3. The integrated circuit of claim 2 , wherein the task manager circuit is further configured to:
detect completion of the first task; and
based on the completion of the first task, provide the second address to the processor core.
4. The integrated circuit of claim 2 , wherein the task manager circuit is further configured to, based on the second indication, cause a set of arithmetic logic unit flags associated with the second task to be stored in the memory.
5. The integrated circuit of claim 2 , wherein the task manager circuit is configured to cause the processor core to resume the first task by interrupting execution of the second task based on a priority of the first task being greater than a priority of the second task.
6. A method comprising:
executing a first task using a processor core;
receiving a first indication from a spinlock circuit that a resource associated with the first task is not available;
based on the first indication, interrupting execution of the first task to execute a second task using the processor core and a first program counter;
receiving a second indication from the spinlock circuit that the resource associated with the first task is available;
based on the second indication, resuming the execution of the first task by:
loading an address associated with the first task into a second program counter; and
causing the processor core to switch from using the first program counter to using the second program counter.
7. The method of claim 6 , wherein:
the address is a first address; and
the resuming of the execution of the first task includes storing a second address in the first program counter to a memory.
8. The method of claim 7 further comprising, based on completion of the first task, resuming the second task by reading the second address from the memory.
9. The method of claim 7 wherein the resuming of the execution of the first task includes storing a set of arithmetic logic unit flags associated with the second task in the memory.
10. The method of claim 6 , wherein the resuming of the execution of the first task interrupts execution of the second task based on a priority of the first task being greater than a priority of the second task.
11. A circuit device comprising:
a processor core that includes a set of program counters that includes a first program counter and a second program counter;
a task manager circuit coupled to the processor core; and
a spinlock circuit coupled to the task manager circuit, wherein:
the processor core is configured to:
execute a first task; and
based on a first indication from the spinlock circuit that a resource associated with the first task is not available, interrupt execution of the first task to execute a second task using a first program counter of the set of program counters; and
the task manager circuit is configured to:
receive a second indication from the spinlock circuit that the resource is available; and
based on the second indication, cause the processor core to resume the first task by:
causing an address associated with the first task to be loaded into a second program counter of the set of program counters; and
causing the address to be copied from the second program counter to the first program counter.
12. The circuit device of claim 11 , wherein:
the address is a first address; and
the circuit device further comprises a memory coupled to the task manager circuit; and
the task manager circuit is configured to, based on the second indication, cause a second address stored in the first program counter to be stored in the memory.
13. The circuit device of claim 12 , wherein the task manager circuit is further configured to:
detect completion of the first task; and
based on the completion of the first task, provide the second address to the processor core.
14. The circuit device of claim 12 , wherein the task manager circuit is further configured to, based on the second indication, cause a set of arithmetic logic unit flags associated with the second task to be stored in the memory.
15. The circuit device of claim 12 , wherein the task manager circuit is configured to cause the processor core to resume the first task by interrupting execution of the second task based on a priority of the first task being greater than a priority of the second task.