Bit line sense amplifier and memory device including the same
A bit line sense amplifier includes a first inverter having an output terminal connected to a complementary sensing bit line, a second inverter having an output terminal connected to a sensing bit line, a first offset element connecting a bit line to the complementary sensing bit line and a second offset element connecting a complementary bit line to the sensing bit line, in response to an offset cancellation signal. During a first time interval, the first offset element and the second offset element are turned off and a capacitor of a first memory cell is connected to the bit line. During a second time interval after the first time interval, the first offset element and the second offset element are turned on and the capacitor of the first memory cell is disconnected from the bit line.
1. A memory device comprising:
a memory cell array including a plurality of memory cells;
a plurality of bit line sense amplifiers connected to the plurality of memory cells through a plurality of bit lines and a plurality of complementary bit lines; and
a control logic configured to control the plurality of bit line sense amplifiers to execute a first read operation and a second read operation of reading data stored in a portion of the plurality of memory cells,
wherein the plurality of bit line sense amplifiers are configured to:
in the first read operation, invert the data stored in the portion of the plurality of memory cells, and output the inverted data, and
in the second read operation, output the data stored in the portion of the plurality of memory cells.
2. The memory device of claim 1 , wherein the control logic is configured to execute a NOT operation for the data stored in the portion of the plurality of memory cells by executing the first read operation.
3. The memory device of claim 1 , wherein the plurality of memory cells are connected to a plurality of word lines, and
wherein when intensive access to a first word line of the plurality of word lines occurs, the control logic is configured to store data obtained by executing the first read operation for a first set of memory cells connected to the first word line in the first set of memory cells.
4. The memory device of claim 1 , wherein the control logic is configured to execute the first read operation or the second read operation based on the number of 1s included in the data stored in the portion of the plurality of memory cells.
5. The memory device of claim 4 , wherein the control logic is configured to:
execute the first read operation when the number of 1s included in the data stored in the portion of the plurality of memory cells is greater than the number of 0s included in the data, and
execute the second read operation when the number of 0s included in the data stored in the portion of the plurality of memory cells is greater than the number of 1s included in the data.
6. The memory device of claim 1 , wherein the control logic is configured to:
control the plurality of bit line sense amplifiers to sequentially obtain first data and second data of n bits from the plurality of memory cells, and
execute the first read operation or the second read operation based on a difference between bits included in each of the first data and the second data.
7. The memory device of claim 6 , wherein the control logic is configured to execute the first read operation or the second read operation so that the difference between the bits included in each of the first data and the second data is minimized.
8. The memory device of claim 1 , wherein the control logic is configured to execute the first read operation for a memory cell having data ‘1’ from among at least some of the plurality of memory cells when the memory device receives a zeroing command for the at least some of the plurality of memory cells.