Memory device and read operation during suspension of program operation thereof

1. A memory device, comprising:

an array of memory cells comprising a first memory cell and a second memory cell; and

a peripheral circuit coupled to the array of memory cells and comprising:

a page buffer comprising at least a page buffer circuit that is coupled to the first and second memory cells, respectively, the page buffer circuit comprising a sensing storage unit and a cache storage unit; and

control logic coupled to the page buffer and configured to:

suspend a program operation on the first memory cell responsive to receiving a suspension command indicative of executing a read operation on the second memory cell;

control the page buffer circuit to store suspended program information associated with a suspension of the program operation;

control the page buffer circuit to release the sensing storage unit and the cache storage unit from being occupied by the suspension of the program operation through a storage of a piece of program information from the suspended program information in a memory controller; and

initiate the read operation on the second memory cell using the sensing storage unit and the cache storage unit.

2. The memory device of claim 1 , wherein the control logic is further configured to:

responsive to a completion of the read operation, control the page buffer circuit to restore the suspended program operation based on the piece of program information received from the memory controller; and

control the page buffer circuit to resume the program operation on the first memory cell using the suspended program information.

3. The memory device of claim 2 , wherein:

the program operation is configured to write a piece of N-bits data at one of 2 N levels to the first memory cell, wherein the piece of N-bits data comprises N portions of page data, and N is an integer greater than 1; and

the suspended program information comprises the N portions of page data and inhibit information associated with the program operation.

4. The memory device of claim 3 , wherein:

the page buffer circuit further comprises a bit line storage unit and N−1 data storage units; and

to control the page buffer circuit to store the suspended program information, the control logic is configured to:

control the page buffer circuit to store the N portions of page data and the inhibit information in N+1 storage units from the sensing storage unit, the bit line storage unit, the N−1 data storage units, and the cache storage unit, respectively.

5. The memory device of claim 4 , wherein to control the page buffer circuit to release the sensing storage unit and the cache storage unit from being occupied by the suspension of the program operation through the storage of the piece of program information in the memory controller, the control logic is configured to:

select one of the inhibit information and the N portions of page data as the piece of program information to be stored in the memory controller;

control the page buffer circuit to send the piece of program information to the memory controller for storage; and

control the page buffer circuit to store a remaining portion of the inhibit information and the N portions of page data in the bit line storage unit and the N−1 data storage units, respectively.

6. The memory device of claim 4 , wherein to control the page buffer circuit to release the sensing storage unit and the cache storage unit from being occupied by the suspension of the program operation through the storage of the piece of program information in the memory controller, the control logic is configured to:

determine the piece of program information that is pre-stored in the memory controller, wherein the piece of program information comprises one of the inhibit information and the N portions of page data; and

control the page buffer circuit to store a remaining portion of the inhibit information and the N portions of page data in the bit line storage unit and the N−1 data storage units, respectively.

7. The memory device of claim 5 , wherein:

the piece of program information comprises one of the N portions of page data; and

to control the page buffer circuit to store the remaining portion of the inhibit information and the N portions of page data in the bit line storage unit and the N−1 data storage units, respectively, the control logic is configured to:

control the page buffer circuit to store the inhibit information in the bit line storage unit; and

control the page buffer circuit to store N−1 remaining portions of page data in the N−1 data storage units, respectively.

8. The memory device of claim 5 , wherein:

the piece of program information comprises the inhibit information; and

to control the page buffer circuit to store the remaining portion of the inhibit information and the N portions of page data in the bit line storage unit and the N−1 data storage units, respectively, the control logic is further configured to:

control the page buffer circuit to store the N portions of page data in the bit line storage unit and the N−1 data storage units, respectively.

9. The memory device of claim 4 , wherein to control the page buffer circuit to restore the suspended program information responsive to the completion of the read operation, the control logic is configured to:

control the page buffer circuit to receive the piece of program information from the memory controller to recover the inhibit information and the N portions of page data in the page buffer circuit; and

control the page buffer circuit to re-save the N portions of page data and the inhibit information in the N+1 storage units from the sensing storage unit, the bit line storage unit, the N−1 data storage units, and the cache storage unit, respectively.

10. The memory device of claim 1 , wherein:

the sensing storage unit is coupled to the second memory cell;

the cache storage unit is coupled to the sensing storage unit and an interface of the memory device; and

to initiate the read operation on the second memory cell, the control logic is configured to:

control the page buffer circuit to store a read signal from the second memory cell in the sensing storage unit;

control the page buffer circuit to send the read signal from the sensing storage unit to the cache storage unit; and

control the page buffer circuit to send the read signal from the cache storage unit to the interface of the memory device.

11. The memory device of claim 1 , wherein the first and second memory cells are in a three-dimensional (3D) NAND memory string.

12. A memory system, comprising:

a memory device configured to store data and comprising:

an array of memory cells comprising a first memory cell and a second memory cell; and

a peripheral circuit coupled to the array of memory cells and comprising:

a page buffer comprising at least a page buffer circuit that is coupled to the first and second memory cells, respectively, the page buffer circuit comprising a sensing storage unit and a cache storage unit; and

control logic coupled to the page buffer and configured to:

suspend a program operation on the first memory cell responsive to receiving a suspension command indicative of executing a read operation on the second memory cell;

control the page buffer circuit to store suspended program information associated with a suspension of the program operation; and

control the page buffer circuit to release the sensing storage unit and the cache storage unit from being occupied by the suspension of the program operation for the read operation on the second memory cell; and

a memory controller coupled to the memory device and configured to store a piece of program information from the suspended program information so that the sensing storage unit and the cache storage unit are released from being occupied by the suspension of the program operation.

13. The memory system of claim 12 , wherein responsive to a completion of the read operation:

the memory controller is further configured to send the piece of program information to the page buffer circuit; and

the control logic is further configured to:

control the page buffer circuit to restore the suspended program operation based on the piece of program information received from the memory controller; and

control the page buffer circuit to resume the program operation on the first memory cell using the suspended program information.

14. The memory system of claim 13 , wherein:

the program operation is configured to write a piece of N-bits data at one of 2 N levels to the first memory cell, wherein the piece of N-bits data comprises N portions of page data, and N is an integer greater than 1; and

the suspended program information comprises the N portions of page data and inhibit information associated with the program operation.

15. The memory system of claim 14 , wherein:

the page buffer circuit further comprises a bit line storage unit and N−1 data storage units; and

to control the page buffer circuit to store the suspended program information, the control logic is configured to:

control the page buffer circuit to store the N portions of page data and the inhibit information in N+1 storage units from the sensing storage unit, the bit line storage unit, the N−1 data storage units, and the cache storage unit, respectively.

16. The memory system of claim 15 , wherein to control the page buffer circuit to release the sensing storage unit and the cache storage unit from being occupied by the suspension of the program operation for the read operation on the second memory cell, the control logic is configured to:

control the page buffer circuit to release the sensing storage unit and the cache storage unit from being occupied by the suspension of the program operation through a storage of the piece of program information on the memory controller.

17. The memory device of claim 16 , wherein the control logic is further configured to initiate the read operation on the second memory cell using the sensing storage unit and the cache storage unit.

18. The memory system of claim 16 , wherein to control the page buffer circuit to release the sensing storage unit and the cache storage unit from being occupied by the suspension of the program operation through the storage of the piece of program information on the memory controller, the control logic is configured to:

select one of the inhibit information and the N portions of page data as the piece of program information to be stored in the memory controller;

control the page buffer circuit to send the piece of program information to the memory controller for storage; and

control the page buffer circuit to store a remaining portion of the inhibit information and the N portions of page data in the bit line storage unit and the N−1 data storage units, respectively.

19. The memory system of claim 16 , wherein the memory controller is configured to pre-store the piece of program information before the suspension of the program operation.

20. A method for operating a memory device comprising an array of memory cells, the array of memory cells comprising a first memory cell and a second memory cell that are coupled to a page buffer circuit in a page buffer, the page buffer circuit comprising a sensing storage unit and a cache storage unit, the method comprising:

suspending a program operation on the first memory cell responsive to receiving a suspension command indicative of executing a read operation on the second memory cell;

controlling the page buffer circuit to store suspended program information associated with a suspension of the program operation;

controlling the page buffer circuit to release the sensing storage unit and the cache storage unit from being occupied by the suspension of the program operation through a storage of a piece of program information from the suspended program information in a memory controller; and

initiating the read operation on the second memory cell using the sensing storage unit and the cache storage unit.