Partial block erase operations in memory devices
Described are systems and methods for performing partial block erase operations. An example memory device comprises: a memory array comprising a plurality of memory cells electrically coupled to a plurality of wordlines; and a controller coupled to the memory array, the controller to perform operations comprising: identifying, in a memory device, a block comprising a plurality of memory cells; estimating, in the block, a number of pages having a predefined program state; determining, based on the number of pages having the predefined program state, an erase verify voltage to be applied to the block; causing an erase operation to be performed with respect to the block; and causing an erase verify operation to be performed, using the erase verify voltage, with respect to the block.
1. A memory device, comprising:
a memory array comprising a first plurality of memory cells electrically coupled to a plurality of wordlines; and
a controller coupled to the memory array, the controller to perform operations comprising:
identifying, in the memory device, a block comprising a second plurality of memory cells;
estimating, in the block, a number of pages having a predefined program state;
determining, based on the number of pages having the predefined program state, an erase verify voltage to be applied to the block;
causing an erase operation to be performed with respect to the block; and
causing an erase verify operation to be performed, using the erase verify voltage, with respect to the block.
2. The memory device of claim 1 , wherein the predefined program state is at least one of: a programmed state or an erased state.
3. The memory device of claim 1 , wherein determining the erase verify voltage further comprises:
determining, based on the number of pages having the predefined program state, an additive voltage adjustment; and
applying the additive voltage adjustment to a base program verify voltage.
4. The memory device of claim 3 , wherein the voltage adjustment is a linear function of the number of pages having the predefined program state.
5. The memory device of claim 1 , wherein estimating the number of pages having the predefined program state further comprises:
identifying, among a plurality of test pages addressable by a plurality of pre-selected wordlines, a first erased page; and
estimating the number of pages having the predefined program state as a linear function of a sequential number of a wordline addressing the first identified erased page.
6. The memory device of claim 1 , wherein estimating the number of pages having the predefined program state further comprises:
identifying a first programmed page of the block; and
estimating the number of pages having the predefined program state as a linear function of a number of the first identified programmed page.
7. The memory device of claim 1 , wherein the operations further comprise:
responsive to detecting a failure of the erase verify operation, modifying at least one erase operation parameter; and
causing a second erase operation to be performed using the modified erase operation parameter.
8. The memory device of claim 1 , wherein causing the erase operation to be performed further comprises:
causing a pre-program voltage to be applied to the plurality of memory cells of the block; and
causing an erase pulse to be applied to the plurality of memory cells of the block.
9. A computer-readable non-transitory storage medium comprising executable instructions that, when executed by a controller managing a memory device comprising a first plurality of memory cells, cause the controller to perform operations, comprising:
identifying, in the memory device, a block comprising a second plurality of memory cells;
estimating, in the block, a number of pages having a predefined program state;
determining, based on the number of pages having the predefined program state, an erase verify voltage to be applied to the block;
causing an erase operation to be performed with respect to the block; and
causing an erase verify operation to be performed, using the erase verify voltage, with respect to the block.
10. The computer-readable non-transitory storage medium of claim 9 , wherein the predefined program state is at least one of: a programmed state or an erased state.
11. The computer-readable non-transitory storage medium of claim 9 , wherein determining the erase verify voltage further comprises:
determining, based on the number of pages having the predefined program state, an additive voltage adjustment; and
applying the additive voltage adjustment to a base program verify voltage.
12. The computer-readable non-transitory storage medium of claim 11 , wherein the voltage adjustment is a linear function of the number of pages having the predefined program state.
13. The computer-readable non-transitory storage medium of claim 9 , wherein estimating the number of pages having the predefined program state further comprises:
identifying, among a plurality of test pages addressable by a plurality of pre-selected wordlines, a first erased page; and
estimating the number of pages having the predefined program state as a linear function of a sequential number of a wordline addressing the first identified erased page.
14. The computer-readable non-transitory storage medium of claim 9 , wherein estimating the number of pages having the predefined program state further comprises:
identifying a first programmed page of the block; and
estimating the number of pages having the predefined program state as a linear function of a number of the first identified programmed page.
15. The computer-readable non-transitory storage medium of claim 9 , wherein the operations further comprise:
responsive to detecting a failure of the erase verify operation, modifying at least one erase operation parameter; and
causing a second erase operation to be performed using the modified erase operation parameter.
16. The computer-readable non-transitory storage medium of claim 9 , wherein causing the erase operation to be performed further comprises:
causing a pre-program voltage to be applied to the plurality of memory cells of the block; and
causing an erase pulse to be applied to the plurality of memory cells of the block.
17. A method, comprising:
identifying, in a memory device, a block comprising a plurality of memory cells;
estimating, in the block, a number of pages having a predefined program state;
determining, based on the number of pages having the predefined program state, an erase verify voltage to be applied to the block;
causing, by a processing device of a controller managing the memory device, an erase operation to be performed with respect to the block; and
causing an erase verify operation to be performed, using the erase verify voltage, with respect to the block.
18. The method of claim 17 , wherein the predefined program state is at least one of: a programmed state or an erased state.
19. The method of claim 17 , wherein determining the erase verify voltage further comprises:
determining, based on the number of pages having the predefined program state, an additive voltage adjustment; and
applying the additive voltage adjustment to a base program verify voltage.
20. The method of claim 17 , wherein estimating the number of pages having the predefined program state further comprises:
identifying, among a plurality of test pages addressable by a plurality of pre-selected wordlines, a first erased page; and
estimating the number of pages having the predefined program state as a linear function of a sequential number of a wordline addressing the first identified erased page.