Memory interface device
Provided is a memory interface device. A memory interface device, comprising: a DQS input buffer configured to receive input data strobe signals and output a first intermediate data strobe signal, the DQS input buffer providing a static offset; an offset control circuit configured to receive the first intermediate data strobe signal and output a second intermediate data strobe signal; and a duty adjustment buffer configured to receive the second intermediate data strobe signal and output a clean data strobe signal, wherein the offset control circuit provides a dynamic offset using the clean data strobe signal.
1. A memory interface device, comprising:
a DQS input buffer configured to receive input data strobe signals and output first intermediate data strobe signals, the DQS input buffer providing a static offset;
an offset control circuit configured to receive the first intermediate data strobe signals and output second intermediate data strobe signals; and
a duty adjustment buffer configured to receive the second intermediate data strobe signals and output clean data strobe signals, wherein
the offset control circuit provides a dynamic offset using the clean data strobe signals,
the offset control circuit includes first and second offset control transistors being turned on according to the clean data strobe signals to change the dynamic offset, and
a turned-on offset control transistor of the first and second offset control transistors pulls down a corresponding node of the DOS input buffer to provide a positive or negative dynamic offset, the corresponding node being connected to the turned-on offset control transistor.
2. The memory interface device of claim 1 , wherein:
when a first clean data strobe signal of the clean data strobe signals is high, the second offset control transistor is turned on.
3. The memory interface device of claim 1 , wherein:
when a second clean data strobe signal of the clean data strobe signals is high, the first offset control transistor is turned on.
4. The memory interface device of claim 1 , wherein:
when a first input data strobe signal of the input data strobe signals is high, the second offset control transistor is turned on.
5. The memory interface device of claim 4 , wherein:
the turned-on second offset control transistor pulls down a second node of the DQS input buffer to provide a positive dynamic offset.
6. The memory interface device of claim 1 , wherein:
when a second input data strobe signal of the input data strobe signals is high, the first offset control transistor is turned on.
7. The memory interface device of claim 6 , wherein:
the turned-on first offset control transistor pulls down a first node of the DQS input buffer to provide a negative dynamic offset.
8. The memory interface device of claim 6 , wherein:
when a first input data strobe signal of the input data strobe signals is low, and the second input data strobe signal changes from high to low, the first offset control transistor is turned on.
9. The memory interface device of claim 1 , wherein:
the static offset is a direct current (DC) offset.
10. The memory interface device of claim 1 , wherein:
the static offset is provided by setting different sizes of symmetric transistors forming a differential structure in the DQS input buffer.
11. The memory interface device of claim 1 , wherein:
the input data strobe signals are differential data strobe signals.
12. The memory interface device of claim 1 , wherein:
the duty adjustment buffer adjusts a duty error due to the static offset.