IP Library › Granted Patent US 12,087,682
Granted Patent B2
US 12,087,682 · App. 16/907,797 · Granted Sep 10, 2024

Power delivery structures

Inventors: Adel Elsherbini (Tempe, AZ); Feras Eid (Chandler, AZ); Georgios Dogiamis (Chandler, AZ); Beomseok Choi (Chandler, AZ); Henning Braunisch (Phoenix, AZ); William Lambert (Tempe, AZ); Krishna Bharath (Chandler, AZ); Johanna Swan (Scottsdale, AZ)
Assignee: Intel Corporation
H01L23/50H01L21/4853H01L21/563H01L23/3185H01L23/367H01L23/481H01L23/562H01L24/16H01L25/0657H01L25/50H05K1/181H01L2224/16227H01L2225/06513H01L2225/06517H01L2225/06541H01L2225/06565H01L2924/18161
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Quick Facts
Patent No.
US 12,087,682
App. No.
16/907,797
Granted
Sep 10, 2024
Kind
B2
Abstract

An integrated circuit assembly may be fabricated having an electronic substrate, an integrated circuit device having a first surface, an opposing second surface, at least one side extending between the first surface and the second surface, and at least one through-substrate via extending into the integrated circuit device from the second surface, wherein the first surface of the integrated circuit device is electrically attached to the electronic substrate; and at least one power delivery route electrically attached to the second surface of the integrated circuit device and to the electronic substrate, wherein the at least one power delivery route is conformal to the side of the integrated circuit device and the first surface of the electronic substrate.

Claims (40)

1. An integrated circuit assembly, comprising:

an electronic substrate having a first surface;

an integrated circuit device having a first surface, an opposing second surface, and at least one side extending between the first surface and the second surface, wherein the first surface of the integrated circuit device is electrically attached to the first surface of the electronic substrate; and

at least one power delivery route electrically attached to the second surface of the integrated circuit device and the first surface of the electronic substrate, wherein the at least one power delivery route is conformal to at least a portion of the at least one side of the integrated circuit device and conformal to at least a portion of the first surface of the electronic substrate, and wherein the at least one power delivery route comprises a plurality of power delivery routes, wherein at least one power delivery route of the plurality of power delivery routes comprises a power supply and wherein at least one power delivery route of the plurality of power delivery routes comprises a ground.

2. The integrated circuit assembly of claim 1 , wherein the integrated circuit device comprises at least one through-substrate via extending into the integrated circuit device from the second surface thereof, and wherein the at least one power delivery route is electrically attached to the at least one through-substrate via.

3. The integrated circuit assembly of claim 1 , wherein the at least one power delivery route is conformal to at least a portion of the second surface of the integrated circuit device.

4. The integrated circuit assembly of claim 1 , further comprising an underfill material between the electronic substrate and the integrated circuit device, wherein the at least one power delivery route is conformal to at least a portion of the underfill material.

5. The integrated circuit assembly of claim 1 , further comprising a stress buffer layer between the at least one power delivery route and the second surface of the integrated circuit device.

6. The integrated circuit assembly of claim 1 , further comprising at least one stacked power delivery route in a stacked configuration with and electrically attached to the at least one power delivery route on the second surface of the integrated circuit device.

7. An electronic system, comprising:

an electronic board having a first surface;

an integrated circuit assembly comprising:

an electronic substrate having a first surface and an opposing second surface and at least one side extending between the first surface and the second surface of the electronic substrate; and

an integrated circuit device having a first surface, an opposing second surface, and at least one side extending between the first surface and the second surface; wherein the first surface of the integrated circuit device is electrically attached to the first surface of the electronic substrate, wherein the second surface of the electronic substrate of the integrated circuit assembly is electrically attached to the first surface of the electronic board, and wherein the integrated circuit device comprises at least one through-substrate via extending into the integrated circuit device from the second surface thereof; and

at least one power delivery route electrically attached to the second surface of the integrated circuit device and electrically attached to the first surface of the electronic board, wherein the at least one power delivery route is conformal to at least a portion of the at least one side of the integrated circuit device, at least a portion of the first surface of the electronic substrate, at least a portion of the at least one side of the electronic substrate, and at least a portion of the first surface of the electronic board, and wherein the at least one power delivery route is electrically attached to the at least one through-substrate via.

8. The electronic system of claim 7 , wherein the at least one power delivery route is conformal to at least a portion of the second surface of the integrated circuit device.

9. The electronic system of claim 7 , further comprising an underfill material between the electronic substrate and the integrated circuit device, wherein the at least one power delivery route is conformal to at least a portion of the underfill material.

10. The electronic system of claim 7 , further comprising a stress buffer layer between the at least one power delivery route and the second surface of the integrated circuit device.

11. The electronic system of claim 7 , wherein the at least one power delivery route is non-linear on the second surface of the integrated circuit device.

12. The electronic system of claim 7 , wherein the at least one power delivery route comprises a plurality of power delivery routes, wherein at least one power delivery route of the plurality of power delivery routes comprises a power supply and wherein at least one power delivery route of the plurality of power delivery routes comprises a ground.

13. The electronic system of claim 7 , further comprising at least one stacked power delivery route in a stacked configuration with and electrically attached to the at least one power delivery route on the second surface of the integrated circuit device.

14. An integrated circuit assembly, comprising:

an electronic substrate having a first surface;

an integrated circuit device having a first surface, an opposing second surface, and at least one side extending between the first surface and the second surface, wherein the first surface of the integrated circuit device is electrically attached to the first surface of the electronic substrate; and

at least one power delivery route electrically attached to the second surface of the integrated circuit device and the first surface of the electronic substrate, wherein the at least one power delivery route is conformal to at least a portion of the at least one side of the integrated circuit device and conformal to at least a portion of the first surface of the electronic substrate, and wherein the at least one power delivery route is non-linear on the second surface of the integrated circuit device.

15. The integrated circuit assembly of claim 14 , wherein the integrated circuit device comprises at least one through-substrate via extending into the integrated circuit device from the second surface thereof, and wherein the at least one power delivery route is electrically attached to the at least one through-substrate via.

16. The integrated circuit assembly of claim 14 , further comprising a stress buffer layer between the at least one power delivery route and the second surface of the integrated circuit device.

17. The integrated circuit assembly of claim 14 , wherein the at least one power delivery route is conformal to at least a portion of the second surface of the integrated circuit device.

18. The integrated circuit assembly of claim 14 , further comprising an underfill material between the electronic substrate and the integrated circuit device, wherein the at least one power delivery route is conformal to at least a portion of the underfill material.

19. The integrated circuit assembly of claim 14 , wherein the at least one power delivery route comprises a plurality of power delivery routes, wherein at least one power delivery route of the plurality of power delivery routes comprises a power supply and wherein at least one power delivery route of the plurality of power delivery routes comprises a ground.

20. The integrated circuit assembly of claim 14 , further comprising at least one stacked power delivery route in a stacked configuration with and electrically attached to the at least one power delivery route on the second surface of the integrated circuit device.

21. An integrated circuit assembly, comprising:

an electronic substrate having a first surface;

an integrated circuit device having a first surface, an opposing second surface, and at least one side extending between the first surface and the second surface, wherein the first surface of the integrated circuit device is electrically attached to the first surface of the electronic substrate;

at least one power delivery route electrically attached to the second surface of the integrated circuit device and the first surface of the electronic substrate, wherein the at least one power delivery route is conformal to at least a portion of the at least one side of the integrated circuit device and conformal to at least a portion of the first surface of the electronic substrate; and

at least one stacked power delivery route in a stacked configuration with and electrically attached to the at least one power delivery route on the second surface of the integrated circuit device.

22. The integrated circuit assembly of claim 21 , wherein the integrated circuit device comprises at least one through-substrate via extending into the integrated circuit device from the second surface thereof, and wherein the at least one power delivery route is electrically attached to the at least one through-substrate via.

23. The integrated circuit assembly of claim 21 , wherein the at least one power delivery route is conformal to at least a portion of the second surface of the integrated circuit device.

24. The integrated circuit assembly of claim 21 , further comprising an underfill material between the electronic substrate and the integrated circuit device, wherein the at least one power delivery route is conformal to at least a portion of the underfill material.

25. The integrated circuit assembly of claim 21 , further comprising a stress buffer layer between the at least one power delivery route and the second surface of the integrated circuit device.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 22, 2020
From: ELSHERBINI, ADEL; EID, FERAS; DOGIAMIS, GEORGIOS; CHOI, BEOMSEOK; BRAUNISCH, HENNING; LAMBERT, WILLIAM; BHARATH, KRISHNA; SWAN, JOHANNA
To: INTEL CORPORATION
Reel/Frame 053001/0695 →
Continuity (1)
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