Data bus signal conditioner and level shifter
A circuit includes signal conditioner circuitry, level shifter circuitry, and state detector and controller circuitry coupled between the signal conditioner circuitry and the level shifter circuitry. The state detector and controller circuitry includes receiver circuitry and a finite state machine coupled to the receiver circuitry. The finite state machine is configured to detect a first data rate from signals, control operation of the signal conditioner circuitry responsive to detecting the first data rate, and control operation of the level shifter circuitry during a second data rate.
1. A circuit comprising:
signal conditioner circuitry;
level shifter circuitry; and
state detector and controller circuitry coupled between the signal conditioner circuitry and the level shifter circuitry and including:
receiver circuitry; and a
finite state machine coupled to the receiver circuitry and configured to:
detect a bus state from signals on a data bus; and
control the signal conditioner circuitry and the level shifter circuitry responsive to the bus state.
2. The circuit of claim 1 , wherein the bus state indicates a first data rate or a second data rate, and the finite state machine is further configured to:
control operation of the signal conditioner circuitry responsive to the first data rate; and
control operation of the level shifter circuitry responsive to the second data rate.
3. The circuit of claim 2 , wherein the first data rate is a high-speed data rate, and the second data rate is a low-speed data rate or a full-speed data rate.
4. The circuit of claim 1 , wherein the finite state machine is a first finite state machine, the circuit further comprising low power state detection circuitry including:
a differential receiver;
a clock and data recovery (CDR) circuit coupled to the differential receiver; and
a second finite state machine coupled to the differential receiver and the CDR circuit and configured to detect a low power state from the signals using a clock signal generated by the CDR circuit.
5. The circuit of claim 4 , wherein:
the CDR circuit is configured to generate the clock signal using a synchronization pattern of a packet communicated in the signals; and
the second finite state machine is configured to detect a link power management LPML 1 state using a packet identifier of the packet.
6. The circuit of claim 1 , wherein the signal conditioner circuitry is configured to boost edges of the signals.
7. A system comprising:
a first integrated circuit;
a second integrated circuit; and
an intermediary circuit coupled on a data bus between the first and second integrated circuits, and including:
first switches;
signal conditioner circuitry configured to boost edges of signals on the data bus responsive to the first switches being closed;
second switches;
level shifter circuitry operable responsive to the second switches being closed; and
state detector and controller circuitry including:
receiver circuitry coupled to the data bus; and
a finite state machine coupled to the receiver circuitry and configured to:
detect, from signals received at the receiver circuitry, a bus state; and
operate the first switches and the second switches responsive to the bus state.
8. The system of claim 7 , wherein the first integrated circuit is a first embedded Universal Serial Bus (eUSB2) device and the second integrated circuit is a second eUSB 2 device.
9. The system of claim 7 , wherein the bus state indicates a first data rate or a second data rate, the first data rate is a high-speed data rate, and the second data rate is a low-speed data rate or a full-speed data rate, and the finite state machine is further configured to:
control operation of the signal conditioner circuitry responsive to the first data rate; and
control operation of the level shifter circuitry responsive to the second data rate.
10. The system of claim 7 , wherein the finite state machine is a first finite state machine, the circuit further comprising low power state detection circuitry including:
a differential receiver;
a clock and data recovery (CDR) circuit coupled to the differential receiver; and
a second finite state machine coupled to the differential receiver and the CDR circuit and configured to detect a link power management LPM-L1 (L1) state from the signals using a clock signal generated by the CDR circuit.
11. The system of claim 10 , wherein:
the CDR circuit is configured to generate the clock signal using a synchronization pattern of a packet communicated in the signals; and
the second finite state machine is configured to detect the L1 state using a packet identifier of the packet.
12. A method comprising:
receiving signals on a data bus;
detecting, from the received signals, a bus state of the data bus;
operating, responsive to the bus state of the data bus, signal conditioner circuitry for boosting edges of the received signals and level shifter circuitry for shifting a voltage level of the received signals from a first voltage level to a second voltage level.
13. The method of claim 12 , wherein operating the signal conditioning circuitry and the level shifting circuitry responsive to the bus state, includes:
operating the signal conditioning circuitry responsive to the bus state indicating a high- speed data rate; and
operating the level shifter circuitry responsive to the bus state indicating a low-speed data rate or a full-speed data rate.
14. The method of claim 12 , further comprising operating low power mode detection circuitry responsive to the bus state, for detecting a link power management LPM-L1 (L1) state from the received signals.
15. The method of claim 14 , wherein operating the low power mode detection circuitry includes generating clock signals using a respective synchronization (SYNC) pattern within packets communicated in the received signals.
16. The method of claim 15 , wherein detecting the L 1 state includes:
providing the clock signals to a finite state machine; and
detecting an EXT packet identifier (PID), a SUB PID, and an ACK PID in a succession of the packets, by the finite state machine, using the clock signals.
17. The method of claim 12 , further comprising detecting an embedded Universal Serial Bus single ended one (ESE1) state from the received signals.
18. An intermediary circuit comprising:
a state detector and controller circuit having first and second outputs;
a signal conditioning circuit coupled to the first output; and
a level shifter coupled to the second output;
wherein the state detector and controller circuit is configured to:
receive signals carried on a data bus between communication devices;
detect a bus state of the data bus from the received signals carried on the data bus;
enable the signal conditioning circuit and disable the level shifter responsive to a first detected bus state of the data bus; and
enable the level shifter and disable the signal conditioning circuit responsive to a second detected bus state of the data bus.
19. The intermediary circuit of claim 18 , wherein the first bus state of the data bus is a highspeed data rate, and the second bus state of the data bus is a low-speed data rate or a full-speed data rate.
20. The intermediary circuit of claim 18 , wherein the signal conditioning circuit is configured to boost edges of signals on the data bus.
21. The intermediary circuit of claim 18 , wherein the level shifter is configured to shift voltage levels of signals on the data bus.