Printed circuit board
A printed circuit board according to an embodiment includes a first insulating layer; a second insulating layer disposed on the first insulating layer; and a cavity formed in the first and second insulating layers; wherein the cavity includes a first portion formed in the second insulating layer; and a second portion formed in the first insulating layer; wherein the first portion has a first cross-sectional shape, and wherein the second part has a second cross-sectional shape different from the first cross-sectional shape.
1. A printed circuit board comprising:
a first insulating layer;
a second insulating layer disposed on the first insulating layer;
a cavity formed in the first insulating layer and the second insulating layer;
a first via electrode disposed in the first insulating layer;
a second via electrode including a portion disposed in the second insulating layer;
an intermediate circuit layer disposed between the first via electrode and the portion of the second via electrode; and
a semiconductor device disposed in the cavity,
wherein the first via electrode overlaps the portion of the second via electrode and the intermediate circuit layer in a vertical direction,
wherein the cavity includes a first side wall having a first slope angle and a second side wall having a second slope angle smaller than the first slope angle, and
wherein the semiconductor device overlaps the portion of the second via electrode, the first side wall of the cavity, and the second side wall of the cavity in a horizontal direction perpendicular to the vertical direction.
2. The printed circuit board of claim 1 , comprising:
a third insulating layer disposed on a lower surface of the first insulating layer,
wherein the first slope angle is 90 degrees or less with respect to an upper surface of the third insulating layer, and
wherein the second slope angle is less than 90 degrees with respect to the upper surface of the third insulating layer.
3. The printed circuit board of claim 2 , wherein the first side wall and the second side wall directly contact each other.
4. The printed circuit board of claim 3 , wherein the first side wall and the second side wall directly contact each other at a contact portion, and
wherein the contact portion is lower than the portion of the second via electrode with respect to the upper surface of the third insulating layer.
5. The printed circuit board of claim 3 , wherein the cavity includes a first portion located in the first insulating layer and a second portion located in the second insulating layer,
wherein a width of the first portion of the cavity is largest at a top of the first portion located in a same plane as an upper surface of the first insulating layer,
wherein a width of the second portion of the cavity is largest at a top of the second portion located in a same plane as an upper surface of the second insulating layer, and
wherein the width of the second portion of the cavity at the top of the second portion is greater than the width of the first portion of the cavity at the top of the first portion.
6. The printed circuit board of claim 2 , wherein the first side wall of the cavity has a first height, and the second side wall of the cavity has a second height, and
wherein the first height of the first side wall of the cavity is different from the second height of the second side wall of the cavity.
7. The printed circuit board of claim 6 , wherein the second height is greater than the first height.
8. The printed circuit board of claim 5 , wherein the semiconductor device includes an upper surface and a lower surface, and
wherein the upper surface of the semiconductor device is higher than the upper surface of the second insulating layer with respect to the upper surface of the third insulating layer.
9. The printed circuit board of claim 1 , wherein the first insulating layer includes a recess portion to form the first side wall, and
wherein the second insulating layer includes a through hole to form the second side wall.
10. The printed circuit board of claim 1 , wherein the cavity overlaps the intermediate circuit layer in the horizontal direction.
11. A semiconductor package substrate comprising:
a first insulating layer including an upper surface and a lower surface;
a second insulating layer disposed on the upper surface of the first insulating layer;
a third insulating layer disposed on the lower surface of the first insulating layer;
a cavity formed in the first insulating laser and the second insulating layer;
a first via electrode disposed in the first insulating layer;
a second via electrode including a portion disposed in the second insulating layer;
an intermediate circuit layer disposed between the first via electrode and the portion of the second via electrode; and
a semiconductor device disposed in the cavity,
wherein the first via electrode overlaps the portion of the second via electrode and the intermediate circuit layer in a vertical direction,
wherein the cavity includes a first side wall having a first slope angle and a second side wall having a second slope angle smaller than the first slope angle with respect to an upper surface of the third insulating layer, and
wherein the semiconductor device overlaps the portion of the second via electrode, the first side wall of the cavity, and the second side wall of the cavity in a horizontal direction perpendicular to the vertical direction.
12. The semiconductor package substrate of claim 11 , wherein the first side wall and the second side wall directly contact each other.
13. The semiconductor package substrate of claim 12 , wherein the first side wall and the second side wall directly contact each other at a contact portion, and
wherein the contact portion is lower than the portion of the second via electrode with respect to the upper surface of the third insulating layer.
14. The semiconductor package substrate of claim 11 , wherein the first slope angle is 90 degrees or less with respect to the upper surface of the third insulating layer, and
wherein the second slope angle is less than 90 degrees with respect to the upper surface of the third insulating layer.
15. The semiconductor package substrate of claim 14 , wherein the cavity overlaps the intermediate circuit layer in the horizontal direction.
16. The semiconductor package substrate of claim 15 , wherein the semiconductor device includes an upper surface and a lower surface, and
wherein the upper surface of the semiconductor device is higher than an upper surface of the second insulating layer with respect to the upper surface of the third insulating layer.