Metal layers for increasing polarization of ferroelectric memory device
Various embodiments of the present disclosure are directed towards an integrated chip including a semiconductor layer overlying a substrate. A ferroelectric layer overlies the substrate. A pair of source/drain structures are disposed on the semiconductor layer. A lower metal layer is disposed along a lower surface of the ferroelectric layer. An upper metal layer is disposed along an upper surface of the ferroelectric layer.
1. A method for forming an integrated chip, the method comprising:
depositing a lower metal layer over a substrate;
depositing a ferroelectric layer on the lower metal layer;
depositing an upper metal layer on the ferroelectric layer;
depositing a semiconductor layer on the upper metal layer;
forming a pair of source/drain structures on the semiconductor layer; and
wherein a coefficient of thermal expansion (CTE) of the ferroelectric layer is greater than a CTE of the upper metal layer and a CTE of the lower metal layer.
2. The method of claim 1 , further comprising:
performing an annealing process on the lower metal layer, the ferroelectric layer, and the upper metal layer.
3. The method of claim 2 , further comprising:
performing a fast cooling process on the lower metal layer, the ferroelectric layer, and the upper metal layer after the annealing process.
4. The method of claim 1 , further comprising:
performing a patterning process on the ferroelectric layer, the upper metal layer, and the semiconductor layer such that opposing sidewalls of the semiconductor layer are aligned with opposing sidewalls of the upper metal layer.
5. The method of claim 3 , wherein the annealing process includes exposing the lower metal layer, the ferroelectric layer, and the upper metal layer to a first temperature within a range of about 300 to 700 degrees Celsius for a first duration.
6. The method of claim 5 , wherein the fast cooling process includes reducing the first temperature to a second temperature within a second duration, wherein the second duration is less than the first duration.
7. The method of claim 6 , wherein the second temperature is within a range of about 0 to 150 degrees Celsius, wherein the second duration is about 20 seconds or less.
8. The method of claim 1 , further comprising:
depositing a lower dielectric layer over the substrate;
patterning the lower dielectric layer to define an opening in the lower dielectric layer, wherein the lower metal layer is deposited in the opening; and
performing a planarization process on the lower metal layer.
9. The method of claim 1 , wherein the lower metal layer and the upper metal layer comprise a same material.
10. A method for forming an integrated chip, the method comprising:
depositing a lower metal layer over a substrate;
depositing a ferroelectric layer on the lower metal layer;
depositing an upper metal layer on the ferroelectric layer;
depositing a semiconductor layer on the upper metal layer;
performing an annealing process on the lower metal layer, the ferroelectric layer, and the upper metal layer;
forming a pair of source/drain structures on the semiconductor layer; and
wherein a coefficient of thermal expansion (CTE) of the ferroelectric layer is greater than a CTE of the upper metal layer and a CTE of the lower metal layer.
11. The method of claim 10 , further comprising:
performing a fast cooling process on the lower metal layer, the ferroelectric layer, and the upper metal layer after the annealing process, wherein the annealing process is performed for a first duration and the fast cooling process is performed for a second duration less than the first duration.
12. The method of claim 11 , wherein the annealing process includes increasing a temperature of an environment of the lower metal layer, the ferroelectric layer, and the upper metal layer to a first temperature, wherein the fast cooling process reduces the temperature of the environment to a second temperature that is at least half the first temperature.
13. The method of claim 10 , wherein the upper metal layer has a [ 111 ] crystal orientation.
14. The method of claim 10 , wherein the pair of source/drain structures are spaced between outer sidewalls of the lower metal layer.
15. The method of claim 10 , wherein a thickness of the lower metal layer is greater than a thickness of the ferroelectric layer.
16. A method for forming an integrated chip, the method comprising:
depositing a lower metal layer over a substrate;
depositing a ferroelectric layer on the lower metal layer;
depositing an upper metal layer on the ferroelectric layer;
depositing a semiconductor layer on the upper metal layer;
performing a patterning process on the ferroelectric layer, the upper metal layer, and the semiconductor layer such that opposing sidewalls of the semiconductor layer are aligned with opposing sidewalls of the upper metal layer;
forming a pair of source/drain structures on the semiconductor layer; and
wherein a coefficient of thermal expansion (CTE) of the ferroelectric layer is greater than a CTE of the upper metal layer and a CTE of the lower metal layer.
17. The method of claim 16 , wherein opposing sidewalls of the lower metal layer are aligned with the opposing sidewalls of the semiconductor layer.
18. The method of claim 16 , wherein forming the pair of source/drain structures comprises:
depositing a dielectric layer over the semiconductor layer;
patterning the dielectric layer to form openings in the dielectric layer over the semiconductor layer;
depositing a conductive material on the dielectric layer and in the openings; and
performing a planarization process on the conductive material.
19. The method of claim 16 , wherein thicknesses of the upper metal layer and the lower metal layer are respectively greater than 50 nanometers.
20. The method of claim 16 , wherein the lower metal layer and the upper metal layer respectively comprise a same conductive material.