Method and apparatus for processing matrix data through relaxed pruning

1. An operating method of a matrix data processing apparatus, comprising:

with respect to each of one or more elements included in a processing element array matrix, when a value of each element satisfies a designated condition, determining the element to be a don't-care element and determining an output value of the don't-care element;

generating a bitstream based on the output value of the don't-care element and index values of valid elements included in the matrix;

equally dividing the bitstream, in accordance with a frequency divider, into pieces of a designated number, and generating a Huffman code, based at least in part on a Huffman decoder in conjunction with a multi-level Huffman look up table (LUT) stored in a memory device, corresponding to each of a plurality of lower bitstreams that are generated as a result of the equal division;

updating a state of a gate based on the generated Huffman code; and

displaying, by a display communicatively coupled to a communication module, a first data in accordance with the updated state of the gate.

2. The matrix data processing method as claimed in claim 1 , wherein:

each of the valid elements is a non-zero element, and

the determining of the output value of the don't-care element includes, when the value of the element is greater than a first threshold value and less than a second threshold value, changing the element into the don't-care element and determining the output value of the don't-care element as a value of an invalid element or the don't-care element.

3. The matrix data processing method as claimed in claim 1 , wherein:

the bitstream includes bits, the number of which is equal to a number of elements in the matrix, and

the generating of the bitstream includes generating a bitstream including 1 bits corresponding to indices of the valid elements and 0 bits corresponding to indices of invalid elements.

4. A matrix data processing apparatus comprising:

a processing element (PE) array;

a data buffer;

a control logic;

a Huffman decoder;

a frequency divider; and

a processor, the processor being configured to:

distribute, in accordance with the control logic, a data flow from an external memory into the PE array via the data buffer, the PE array comprising a plurality of elements:

determine each element of the PE array to be a don't-care element when a value of the element satisfies a designated condition;

determine an output value of the don't-care element as an element value of an invalid element or the don't-care element;

generate a bitstream based on the output value of the don't-care element and index values of valid elements included in the matrix;

equally divide, based at least in part on the frequency divider, the bitstream into a designated number of pieces;

generate, based at least in part on the Huffman decoder in conjunction with a multi-level Huffman look up table (LUT) stored in a memory device, a Huffman code corresponding to each of a plurality of lower bitstreams that are obtained as a result of the equal division;

update a state of a gate based on the generated Huffman code; and

display, by a display communicatively coupled to a communication module, a first data.

5. The matrix data processing apparatus as claimed in claim 4 , wherein:

the processor is further configured to generate a Huffman tree corresponding to the Huffman code, and the multi-level LUT further includes look-up tables respectively corresponding to levels in the Huffman tree, and

a number of look-up tables corresponding to an n-th level of the Huffman tree is greater than a number of look-up tables corresponding to an n+1st level of the Huffman tree.

6. The matrix data processing apparatus as claimed in claim 4 , wherein:

each of the valid elements is a non-zero element, and

the processor is further configured to, when the value of the element is greater than a first threshold value and less than a second threshold value, change the element into the don't-care element.

7. The matrix data processing apparatus as claimed in claim 4 , wherein:

the bitstream includes bits, the number of which is equal to a number of elements in the matrix, and

the processor is further configured to generate a bitstream including 1 bits corresponding to indices of the valid elements and 0 bits corresponding to indices of the invalid elements.

8. A non-transitory computer-readable recording medium comprising instructions which, when executed, cause a computer to execute the method according to claim 1 .