Device, method and system for provisioning a real branch instruction and a fake branch instruction to respective decoders
Techniques and mechanisms for providing branch prediction information to facilitate instruction decoding by a processor. In an embodiment, entries of a branch prediction table (BTB) each identify, for a corresponding instruction, whether a prediction based on the instruction (if any) is eligible to be communicated, with another prediction, in a single fetch cycle. A branch prediction unit of the processor determines a linear address of a fetch region which is under consideration, and performs a search of the BTB based on the linear address. A result of the search is evaluated to detect for any hit entry which indicates a double prediction eligibility. In another embodiment, where it is determined that double prediction eligibility is indicated for an earliest one the instructions represented by the hit entries, multiple predictions are communicated in a single fetch cycle.
1. An integrated circuit comprising:
first circuitry to determine that a branch predict table (BTB) is to provide a first entry which corresponds to a first instruction, wherein the first circuitry is to identify first address information which corresponds to the first instruction;
second circuitry, coupled to the first circuitry, to perform an evaluation, based on a classification of the first instruction as one of a fake branch instruction type, to detect whether the BTB includes another entry which corresponds both to the first address information, and to a respective instruction which is of the fake branch instruction type; and
third circuitry, coupled to the second circuitry, to provide a first double prediction eligibility state (DPES) parameter of the first entry based on the evaluation, wherein, for each entry of multiple entries of the BTB, a respective DPES parameter of the entry specifies a presence or an absence of a respective eligibility of a prediction, based on the instruction which corresponds to the entry, to be provided in a same fetch cycle with another prediction based on another instruction.
2. The integrated circuit of claim 1 , further comprising fourth circuitry to:
perform a search of the BTB based on a linear address which corresponds to a fetch region under consideration, wherein the search identifies one or more entries of the BTB; and
send one or more predictions, during a single fetch cycle, each to a respective branch prediction queue, wherein a total number of the one or more predictions is based on one or more DPES parameters of the one or more entries.
3. The integrated circuit of claim 2 , wherein the fourth circuitry is to:
detect a condition wherein two entries of the BTB are hit by the search, wherein the respective DPES parameter of one of the two entries indicates the presence of the respective eligibility, and wherein the respective DPES parameter of the other of the two entries indicates the absence of the respective eligibility; and
determine, based on the condition, whether the one of the two entries comes before the other of the two entries in a sequence of instructions.
4. The integrated circuit of claim 3 , wherein, where the one of the two entries comes before the other of the two entries in the sequence of instructions, the fourth circuitry is to send two predictions during the single fetch cycle based on the search.
5. The integrated circuit of claim 1 , wherein the second circuitry is to detect a condition wherein, for any entry of the BTB which is detected by the evaluation, the respective DPES parameter of the entry indicates the absence of the respective eligibility; and
wherein, based on the condition, the third circuitry is to indicate with the first DPES parameter the presence of the respective eligibility.
6. The integrated circuit of claim 1 , wherein the second circuitry is to detect a condition wherein, for one entry of the BTB which is detected by the evaluation, the respective DPES parameter of the entry indicates the presence of the respective eligibility; and
wherein, based on the condition, the third circuitry is to indicate with the first DPES parameter the absence of the respective eligibility.
7. The integrated circuit of claim 1 , wherein the BTB is a set associative BTB comprising sets and ways, and wherein the first circuitry to identify the first address information comprises the first circuitry to generate, based on an address corresponding to the first instruction:
a tag value corresponding to one of the sets; and
an index value corresponding to one or more ways of the one of the sets; and
wherein the second circuitry is to perform the evaluation to detect whether the BTB includes another entry which corresponds to the tag value and to the index value.
8. A method comprising:
determining that a branch predict table (BTB) is to provide a first entry which corresponds to a first instruction, including identifying first address information which corresponds to the first instruction;
performing an evaluation, based on a classification of the first instruction as one of a fake branch instruction type, to detect whether the BTB includes another entry which corresponds both to the first address information, and to a respective instruction which is of the fake branch instruction type; and
providing a first double prediction eligibility state (DPES) parameter of the first entry based on the evaluation, wherein, for each entry of multiple entries of the BTB, a respective DPES parameter of the entry specifies a presence or an absence of a respective eligibility of a prediction, based on the instruction which corresponds to the entry, to be provided in a same fetch cycle with another prediction based on another instruction.
9. The method of claim 8 , further comprising:
performing a search of the BTB based on a linear address which corresponds to a fetch region under consideration, wherein the search identifies one or more entries of the BTB; and
sending one or more predictions, during a single fetch cycle, each to a respective branch prediction queue, wherein a total number of the one or more predictions is based on one or more DPES parameters of the one or more entries.
10. The method of claim 9 , wherein performing the search comprises:
detecting a condition wherein two entries of the BTB are hit by the search, wherein the respective DPES parameter of one of the two entries indicates the presence of the respective eligibility, and wherein the respective DPES parameter of the other of the two entries indicates the absence of the respective eligibility; and
determining, based on the condition, whether the one of the two entries comes before the other of the two entries in a sequence of instructions.
11. The method of claim 9 , wherein performing the search comprises detecting a condition wherein only one entry of the BTB is hit by the search, and
wherein, based on the condition, only one prediction is sent during the single fetch cycle based on the search.
12. The method of claim 8 , wherein performing the evaluation comprises detecting a condition wherein, for any entry of the BTB which is detected by the evaluation, the respective DPES parameter of the entry indicates the absence of the respective eligibility; and
wherein, based on the condition, the first DPES parameter indicates the presence of the respective eligibility.
13. The method of claim 8 , wherein performing the evaluation comprises detecting a condition wherein, for one entry of the BTB which is detected by the evaluation, the respective DPES parameter of the entry indicates the presence of the respective eligibility; and
wherein, based on the condition, the first DPES parameter indicates the absence of the respective eligibility.
14. The method of claim 8 , wherein the BTB is a set associative BTB comprising sets and ways, and wherein identifying the first address information comprises generating, based on an address corresponding to the first instruction:
a tag value corresponding to one of the sets; and
an index value corresponding to one or more ways of the one of the sets; and
wherein the evaluation is to detect whether the BTB includes another entry which corresponds to the tag value and to the index value.
15. A system comprising:
a processor comprising:
branch predict table (BTB);
first circuitry to determine that the BTB is to provide a first entry which corresponds to a first instruction, wherein the first circuitry is to identify first address information which corresponds to the first instruction;
second circuitry, coupled to the first circuitry, to perform an evaluation, based on a classification of the first instruction as one of a fake branch instruction type, to detect whether the BTB includes another entry which corresponds both to the first address information, and to a respective instruction which is of the fake branch instruction type; and
third circuitry, coupled to the second circuitry, to provide a first double prediction eligibility state (DPES) parameter of the first entry based on the evaluation, wherein, for each entry of multiple entries of the BTB, a respective DPES parameter of the entry specifies a presence or an absence of a respective eligibility of a prediction, based on the instruction which corresponds to the entry, to be provided in a same fetch cycle with another prediction based on another instruction; and
a display device coupled to the processor, the display device to display an image based on a signal communicated with the processor.
16. The system of claim 15 , the processor further comprising fourth circuitry to:
perform a search of the BTB based on a linear address which corresponds to a fetch region under consideration, wherein the search identifies one or more entries of the BTB; and
send one or more predictions, during a single fetch cycle, each to a respective branch prediction queue, wherein a total number of the one or more predictions is based on one or more DPES parameters of the one or more entries.
17. The system of claim 16 , wherein the fourth circuitry is to:
detect a condition wherein two entries of the BTB are hit by the search, wherein the respective DPES parameter of one of the two entries indicates the presence of the respective eligibility, and wherein the respective DPES parameter of the other of the two entries indicates the absence of the respective eligibility; and
determine, based on the condition, whether the one of the two entries comes before the other of the two entries in a sequence of instructions.
18. The system of claim 15 , wherein the second circuitry is to detect a condition wherein, for any entry of the BTB which is detected by the evaluation, the respective DPES parameter of the entry indicates the absence of the respective eligibility; and
wherein, based on the condition, the third circuitry is to indicate with the first DPES parameter the presence of the respective eligibility.
19. The system of claim 15 , wherein the second circuitry is to detect a condition wherein, for one entry of the BTB which is detected by the evaluation, the respective DPES parameter of the entry indicates the presence of the respective eligibility; and
wherein, based on the condition, the third circuitry is to indicate with the first DPES parameter the absence of the respective eligibility.
20. The system of claim 15 , wherein the BTB is a set associative BTB comprising sets and ways, and wherein the first circuitry to identify the first address information comprises the first circuitry to generate, based on an address corresponding to the first instruction:
a tag value corresponding to one of the sets; and
an index value corresponding to one or more ways of the one of the sets; and
wherein the second circuitry is to perform the evaluation to detect whether the BTB includes another entry which corresponds to the tag value and to the index value.