IP Library › Granted Patent US 12,093,736
Granted Patent B2
US 12,093,736 · App. 17/439,821 · Granted Sep 17, 2024

Pipeline computing apparatus, programmable logic controller, and pipeline processing execution method

Inventors: Koji Nishigaki (Kusatsu, JP); Takaya Shimizu (Kyoto, JP); Takenori Kusaka (Kyoto, JP)
Assignee: OMRON Corporation
G06F9/5027G06F9/50
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Quick Facts
Patent No.
US 12,093,736
App. No.
17/439,821
Granted
Sep 17, 2024
Kind
B2
Abstract

A pipeline computing apparatus ( 110 ) comprises: a computing unit ( 120 ) configured as a pipeline; a node monitoring unit ( 161 ) that obtains a node processing time; a queue monitoring unit ( 162 ) that obtains an accumulated message amount; a priority variable calculating unit ( 163 ) that, on the basis of the node processing time and the accumulated message amount in a reception queue in a stage previous to the node, calculates a priority variable of the node; and a time allocating unit ( 164 ) that allocates operating time to each of nodes in accordance with the priority variable.

Claims (51)

1. A pipeline computing apparatus, comprising:

a computing circuit comprising a plurality of nodes and a plurality of reception queues, and the computing circuit being composed of at least one of pipelines in which a plurality of the nodes are connected via the reception queues; and

a control circuit comprising a node monitoring circuit, a queue monitoring circuit, a priority variable calculating circuit, and a time allocating circuit,

wherein the node monitoring circuit acquires a node processing time, which is a time required to process one message in the node, from the node,

the queue monitoring circuit acquires an accumulated message amount of the reception queue from the reception queue,

the priority variable calculating circuit calculates a priority variable of the node based on at least the node processing time of the node and the accumulated message amount of the reception queue in a stage previous to the node, and

the time allocating circuit allocates an operating time to each node according to the priority variable for each node.

2. The pipeline computing apparatus according to claim 1 , wherein the accumulated message amount is a number of messages accumulated in the reception queue or a total size of the accumulated messages.

3. The pipeline computing apparatus according to claim 2 , wherein the priority variable calculating circuit calculates a product of the node processing time of the node and the accumulated message amount as the priority variable of the node.

4. The pipeline computing apparatus according to claim 2 , wherein the priority variable calculating circuit generates the node processing time for calculating the priority variable of the node based on a plurality of previous node processing times of the node acquired by the node monitoring circuit.

5. The pipeline computing apparatus according to claim 2 , wherein the computing circuit further comprises a merger monitoring circuit and a correction coefficient calculating circuit,

for a pipeline in which a plurality of partial pipelines merge among the pipelines, the merger monitoring circuit acquires from the queue monitoring circuit accumulated message amounts of reception queues in a stage previous to nodes belonging to different partial pipelines upstream of a node at a merger point of the plurality of partial pipelines, and calculates a determination of imbalance in the accumulated message amounts of the reception queues in the stage previous to the nodes belonging to the different partial pipelines,

the correction coefficient calculating circuit calculates a correction coefficient according to the determination of imbalance for the node belonging to any of the partial pipelines among the different partial pipelines, and

when the correction coefficient is calculated for the node, the time allocating circuit allocates the operating time according to a value obtained by multiplying the priority variable by the correction coefficient.

6. The pipeline computing apparatus according to claim 2 , wherein the computing circuit further comprises a memory monitoring circuit and a correction coefficient calculating circuit,

when a free capacity of a memory that stores accumulated messages of the reception queue becomes smaller than a predetermined value, the memory monitoring circuit sends a notification to the correction coefficient calculating circuit,

when receiving the notification, the correction coefficient calculating circuit gives a correction coefficient larger than 1 for a node belonging to a pipeline that has a shorter time to complete processing of messages in the pipeline or has fewer branches among the plurality of pipelines, and

when the correction coefficient is given to the node, the time allocating circuit allocates the operating time according to a value obtained by multiplying the priority variable by the correction coefficient.

7. The pipeline computing apparatus according to claim 1 , wherein the priority variable calculating circuit calculates a product of the node processing time of the node and the accumulated message amount as the priority variable of the node.

8. The pipeline computing apparatus according to claim 7 , wherein the priority variable calculating circuit generates the node processing time for calculating the priority variable of the node based on a plurality of previous node processing times of the node acquired by the node monitoring circuit.

9. The pipeline computing apparatus according to claim 7 , wherein the computing circuit further comprises a merger monitoring circuit and a correction coefficient calculating circuit,

for a pipeline in which a plurality of partial pipelines merge among the pipelines, the merger monitoring circuit acquires from the queue monitoring circuit accumulated message amounts of reception queues in a stage previous to nodes belonging to different partial pipelines upstream of a node at a merger point of the plurality of partial pipelines, and calculates a determination of imbalance in the accumulated message amounts of the reception queues in the stage previous to the nodes belonging to the different partial pipelines,

the correction coefficient calculating circuit calculates a correction coefficient according to the determination of imbalance for the node belonging to any of the partial pipelines among the different partial pipelines, and

when the correction coefficient is calculated for the node, the time allocating circuit allocates the operating time according to a value obtained by multiplying the priority variable by the correction coefficient.

10. The pipeline computing apparatus according to claim 7 , wherein the computing circuit further comprises a memory monitoring circuit and a correction coefficient calculating circuit,

when a free capacity of a memory that stores accumulated messages of the reception queue becomes smaller than a predetermined value, the memory monitoring circuit sends a notification to the correction coefficient calculating circuit,

when receiving the notification, the correction coefficient calculating circuit gives a correction coefficient larger than 1 for a node belonging to a pipeline that has a shorter time to complete processing of messages in the pipeline or has fewer branches among the plurality of pipelines, and

when the correction coefficient is given to the node, the time allocating circuit allocates the operating time according to a value obtained by multiplying the priority variable by the correction coefficient.

11. The pipeline computing apparatus according to claim 1 , wherein the priority variable calculating circuit generates the node processing time for calculating the priority variable of the node based on a plurality of previous node processing times of the node acquired by the node monitoring circuit.

12. The pipeline computing apparatus according to claim 11 , wherein the computing circuit further comprises a merger monitoring circuit and a correction coefficient calculating circuit,

for a pipeline in which a plurality of partial pipelines merge among the pipelines, the merger monitoring circuit acquires from the queue monitoring circuit accumulated message amounts of reception queues in a stage previous to nodes belonging to different partial pipelines upstream of a node at a merger point of the plurality of partial pipelines, and calculates a determination of imbalance in the accumulated message amounts of the reception queues in the stage previous to the nodes belonging to the different partial pipelines,

the correction coefficient calculating circuit calculates a correction coefficient according to the determination of imbalance for the node belonging to any of the partial pipelines among the different partial pipelines, and

when the correction coefficient is calculated for the node, the time allocating circuit allocates the operating time according to a value obtained by multiplying the priority variable by the correction coefficient.

13. The pipeline computing apparatus according to claim 11 , wherein the computing circuit further comprises a memory monitoring circuit and a correction coefficient calculating circuit,

when a free capacity of a memory that stores accumulated messages of the reception queue becomes smaller than a predetermined value, the memory monitoring circuit sends a notification to the correction coefficient calculating circuit,

when receiving the notification, the correction coefficient calculating circuit gives a correction coefficient larger than 1 for a node belonging to a pipeline that has a shorter time to complete processing of messages in the pipeline or has fewer branches among the plurality of pipelines, and

when the correction coefficient is given to the node, the time allocating circuit allocates the operating time according to a value obtained by multiplying the priority variable by the correction coefficient.

14. The pipeline computing apparatus according to claim 1 , wherein the computing circuit further comprises a merger monitoring circuit and a correction coefficient calculating circuit,

for a pipeline in which a plurality of partial pipelines merge among the pipelines, the merger monitoring circuit acquires from the queue monitoring circuit accumulated message amounts of reception queues in a stage previous to nodes belonging to different partial pipelines upstream of a node at a merger point of the plurality of partial pipelines, and calculates a determination of imbalance in the accumulated message amounts of the reception queues in the stage previous to the nodes belonging to the different partial pipelines,

the correction coefficient calculating circuit calculates a correction coefficient according to the determination of imbalance for the node belonging to any of the partial pipelines among the different partial pipelines, and

when the correction coefficient is calculated for the node, the time allocating circuit allocates the operating time according to a value obtained by multiplying the priority variable by the correction coefficient.

15. The pipeline computing apparatus according to claim 1 , wherein the computing circuit further comprises a memory monitoring circuit and a correction coefficient calculating circuit,

when a free capacity of a memory that stores accumulated messages of the reception queue becomes smaller than a predetermined value, the memory monitoring circuit sends a notification to the correction coefficient calculating circuit,

when receiving the notification, the correction coefficient calculating circuit gives a correction coefficient larger than 1 for a node belonging to a pipeline that has a shorter time to complete processing of messages in the pipeline or has fewer branches among the plurality of pipelines, and

when the correction coefficient is given to the node, the time allocating circuit allocates the operating time according to a value obtained by multiplying the priority variable by the correction coefficient.

16. A programmable logic controller comprising the pipeline computing apparatus according to claim 1 .

17. A pipeline processing execution method for executing pipeline processing by at least one pipeline in which a plurality of nodes are connected via a plurality of reception queues, the pipeline processing execution method comprising:

a step of acquiring a node processing time, which is a time required to process one message in the node;

a step of acquiring an accumulated message amount of the reception queue;

a step of calculating a priority variable of the node based on at least the node processing time of the node and the accumulated message amount of the reception queue in a stage previous to the node; and

a step of allocating an operating time to each node according to the priority variable for each node.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 15, 2021
From: NISHIGAKI, KOJI; SHIMIZU, TAKAYA; KUSAKA, TAKENORI
To: OMRON CORPORATION
Reel/Frame 057800/0838 →
Priority Claims (1)
JP 2019-053468 · Mar 20, 2019 · national
Continuity (1)
Related Publication 20220179708A1 · Jun 9, 2022