Semiconductor integrated circuit device
In a power line structure for supplying power to standard cells, buried power lines extending in the X direction are placed at a given spacing in the Y direction. A local power line extending in the Y direction is connected with the buried power lines. Metal power lines extending in the X direction are formed in an upper-layer metal interconnect layer and connected with the local power line. The spacing of placement of the metal power lines in the Y direction is greater than the spacing of placement of the buried power lines.
1. A semiconductor integrated circuit device, comprising:
a plurality of cell rows each including standard cells arranged in a first direction, the cell rows being arranged in a second direction vertical to the first direction;
a plurality of buried power lines formed in a buried interconnect layer, extending in the first direction, placed at a first given spacing in the second direction, and supplying a first power supply voltage to the standard cells;
a local power line formed in a local interconnect layer in which local interconnects in contact with sources and drains of transistors included in the standard cells are formed, extending in the second direction, and connected with the plurality of buried power lines; and
a plurality of metal power lines formed in a metal interconnect layer located above the local interconnect layer, extending in the first direction, placed at a second given spacing greater than the first given spacing in the second direction, and connected with the local power line.
2. The semiconductor integrated circuit device of claim 1 , further comprising:
a power tap cell group including a plurality of power tap cells arranged in the second direction, each of the power tap cells being provided in each of the plurality of cell rows,
wherein
the plurality of power tap cells each include a local interconnect extending in the second direction, and
the local power line is formed by continuous placement of the local interconnects of the plurality of power tap cells.
3. The semiconductor integrated circuit device of claim 2 , wherein
the power tap cell group is placed at a plurality of positions equally spaced in the first direction.
4. The semiconductor integrated circuit device of claim 1 , further comprising:
a plurality of second buried power lines formed in the buried interconnect layer, extending in the first direction, placed at a third given spacing in the second direction, and supplying a second power supply voltage to the standard cells;
a second local power line formed in the local interconnect layer, extending in the second direction, and connected with the plurality of second buried power lines; and
a plurality of second metal power lines formed in the metal interconnect layer, extending in the first direction, placed at a fourth given spacing greater than the third given spacing in the second direction, and connected with the second local power line.
5. The semiconductor integrated circuit device of claim 4 , further comprising:
a power tap cell group including a plurality of power tap cells arranged in the second direction, each of the power tap cells being provided in each of the plurality of cell rows,
wherein
the plurality of power tap cells each include first and second local interconnects extending in parallel in the second direction, and
the local power line is formed by continuous placement of the first local interconnects of the plurality of power tap cells, and the second local power line is formed by continuous placement of the second local interconnects of the plurality of power tap cells.
6. The semiconductor integrated circuit device of claim 4 , further comprising:
a first power tap cell group including a plurality of first power tap cells arranged in the second direction, each of the first power tap cells being provided in each of the plurality of cell rows; and
a second power tap cell group including a plurality of second power tap cells arranged in the second direction, each of the second power tap cells being provided in each of the plurality of cell rows,
wherein
the plurality of first power tap cells each include a first local interconnect extending in the second direction,
the plurality of second power tap cells each include a second local interconnect extending in the second direction, and
the local power line is formed by continuous placement of the first local interconnects of the plurality of first power tap cells, and the second local power line is formed by continuous placement of the second local interconnects of the plurality of second power tap cells.
7. The semiconductor integrated circuit device of claim 1 , further comprising:
a plurality of power terminal cells arranged in the second direction at one end of the plurality of cell rows in the first direction, and
the plurality of power terminal cells each include a buried interconnect extending in the second direction for mutually connecting the plurality of buried power lines.
8. A semiconductor integrated circuit device, comprising:
a plurality of cell rows each including standard cells arranged in a first direction, the cell rows being arranged in a second direction vertical to the first direction;
a plurality of buried power lines formed in a buried interconnect layer, extending in the first direction, placed at a first given spacing in the second direction, and supplying a first power supply voltage to the standard cells;
a local power line formed in a local interconnect layer in which local interconnects in contact with sources and drains of transistors included in the standard cells are formed, extending in the second direction, and connected with the plurality of buried power lines; and
a metal power line formed in a metal interconnect layer located above the local interconnect layer, extending in the second direction, and overlapping the local power line as viewed in plan,
wherein
the local power line and the metal power line are mutually connected by a plurality of connecting portions provided at a second given spacing greater than the first given spacing in the second direction.
9. The semiconductor integrated circuit device of claim 8 , further comprising:
a plurality of second buried power lines formed in the buried interconnect layer, extending in the first direction, placed at a third given spacing in the second direction, and supplying a second power supply voltage to the standard cells;
a second local power line formed in the local interconnect layer, extending in the second direction, and connected with the plurality of second buried power lines; and
a second metal power line formed in the metal interconnect layer, extending in the second direction, and overlapping the second local power line as viewed in plan,
wherein
the second local power line and the second metal power line are mutually connected by a plurality of second connecting portions provided at a fourth given spacing greater than the third given spacing in the second direction.
10. The semiconductor integrated circuit device of claim 9 , wherein
the plurality of connecting portions and the plurality of second connecting portions are placed at same positions in the second direction.
11. A semiconductor integrated circuit device, comprising:
a plurality of cell rows each including standard cells arranged in a first direction, the cell rows being arranged in a second direction vertical to the first direction;
a plurality of metal power lines formed in a first metal interconnect layer, extending in the first direction, placed at a first given spacing in the second direction, and supplying a first power supply voltage to the standard cells;
a local power line formed in a local interconnect layer in which local interconnects in contact with sources and drains of transistors included in the standard cells are formed, extending in the second direction, and connected with the plurality of metal power lines;
a buried power line formed in a buried interconnect layer, extending in the second direction, overlapping the local power line as viewed in plan, and connected with the local power line; and
an upper-layer metal power line formed in a second metal interconnect layer located above the first metal interconnect layer, extending in the second direction, and overlapping the local power line as viewed in plan,
wherein
the local power line and the upper-layer metal power line are mutually connected in only cell rows on both ends of the plurality of cell rows in the second direction.
12. The semiconductor integrated circuit device of claim 11 , further comprising:
a power tap cell group including a plurality of power tap cells arranged in the second direction, each of the power tap cells being provided in each of the plurality of cell rows,
wherein
the plurality of power tap cells each include a local interconnect extending in the second direction and a buried interconnect overlapping the local interconnect, and
the local power line is formed by continuous placement of the local interconnects of the plurality of power tap cells, and the buried power line is formed by continuous placement of the buried interconnects of the plurality of power tap cells.
13. The semiconductor integrated circuit device of claim 12 , wherein
the power tap cell group is placed at a plurality of positions equally spaced in the first direction.
14. The semiconductor integrated circuit device of claim 11 , further comprising:
a plurality of second metal power lines formed in the first interconnect layer, extending in the first direction, placed at a third given spacing in the second direction, and supplying a second power supply voltage to the standard cells;
a second local power line formed in the local interconnect layer, extending in the second direction, and connected with the plurality of second metal power lines;
a second buried power line formed in the buried interconnect layer, extending in the second direction, overlapping the second local power line as viewed in plan, and connected with the second local power line; and
a second upper-layer metal power line formed in the second metal interconnect layer, extending in the second direction, and overlapping the second local power line as viewed in plan,
wherein
the second local power line and the second upper-layer metal power line are mutually connected in only cell rows on both ends of the plurality of cell rows in the second direction.