IP Library › Granted Patent US 12,094,908
Granted Patent B2
US 12,094,908 · App. 17/275,242 · Granted Sep 17, 2024

Solid-state imaging device and electronic device

Inventors: Masaaki Takizawa (Kanagawa, JP); Yorito Sakano (Kanagawa, JP)
Assignee: Sony Semiconductor Solutions Corporation
H01L27/14634H01L24/08H01L24/80H01L27/14603H01L27/14621H01L27/14627H01L27/1463H01L27/14636H01L27/1464H01L27/14645H01L27/1469H01L2224/08145H01L2224/80895H01L2224/80896
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 12,094,908
App. No.
17/275,242
Granted
Sep 17, 2024
Kind
B2
Abstract

A wide dynamic range with single exposure is achieved. A solid-state imaging device according to an embodiment includes a first substrate including a photoelectric conversion element, and a second substrate including a capacitor positioned on a side opposite to a surface of incidence of light to the photoelectric conversion element in the first substrate, and configured to accumulate a charge transferred from the photoelectric conversion element.

Claims (46)

1. An electronic device, comprising:

a first substrate including a photoelectric conversion element; and

a second substrate including a capacitor positioned on a side opposite to a surface of incidence of light to the photoelectric conversion element in the first substrate, and configured to accumulate a charge transferred from the photoelectric conversion element,

wherein the first substrate further includes a first copper electrode pad provided on a surface opposite to the surface of incidence,

wherein the second substrate further includes a second copper electrode pad provided on a surface opposed to the first substrate, and

wherein the first substrate and the second substrate are bonded to each other through bonding between the first copper electrode pad and the second copper electrode pad.

2. The electronic device according to claim 1 , wherein the capacitor is a trench capacitor.

3. The electronic device according to claim 1 , wherein:

the first substrate includes a plurality of the photoelectric conversion elements; and

the capacitor is configured to accumulate a charge transferred from at least one of the photoelectric conversion elements.

4. The electronic device according to claim 1 , wherein the capacitor includes a plurality of trench capacitors.

5. A solid-state imaging device, comprising:

a first substrate including a photoelectric conversion element; and

a second substrate including a capacitor positioned on a side opposite to a surface of incidence of light to the photoelectric conversion element in the first substrate, and configured to accumulate a charge transferred from the photoelectric conversion element,

wherein the first substrate further includes a first copper electrode pad provided on a surface opposite to the surface of incidence,

wherein the second substrate further includes a second copper electrode pad provided on a surface opposed to the first substrate, and

wherein the first substrate and the second substrate are bonded to each other through bonding between the first copper electrode pad and the second copper electrode pad.

6. The solid-state imaging device according to claim 5 , wherein the capacitor is a trench capacitor.

7. The solid-state imaging device according to claim 5 , wherein:

the first substrate includes a plurality of the photoelectric conversion elements; and

the capacitor is configured to accumulate a charge transferred from at least one of the photoelectric conversion elements.

8. The solid-state imaging device according to claim 5 , wherein the first substrate further includes a transfer transistor configured to control transfer of a charge from the photoelectric conversion element to the capacitor.

9. The solid-state imaging device according to claim 5 , wherein the capacitor includes a plurality of trench capacitors.

10. The solid-state imaging device according to claim 9 , wherein the trench capacitors are connected to one another in parallel.

11. The solid-state imaging device according to claim 5 , wherein the second substrate further includes a pixel circuit including:

a reset transistor configured to control discharge of the charge accumulated in the capacitor;

an amplification transistor configured to cause, in a drain, a pixel signal of a voltage value that depends on a quantity of the charge accumulated in the capacitor; and

a selection transistor configured to switch connection between the drain of the amplification transistor and a predetermined wiring.

12. The solid-state imaging device according to claim 11 , wherein the capacitor is connected between a gate of the amplification transistor and a ground.

13. The solid-state imaging device according to claim 11 , further comprising a switch transistor with a source connected to a gate of the amplification transistor and a drain connected to a source of the reset transistor,

wherein the capacitor is connected between a ground and a node that connects the source of the reset transistor and the drain of the switch transistor to each other.

14. The solid-state imaging device according to claim 11 , further comprising a third substrate positioned on a side opposite to a surface of the second substrate opposed to the first substrate,

wherein the third substrate includes a circuit element configured to execute predetermined processing for the pixel signal that has appeared in the predetermined wiring.

15. The solid-state imaging device according to claim 14 , wherein the second substrate and the third substrate are bonded to each other by direct bonding.

16. The solid-state imaging device according to claim 14 , wherein:

the second substrate includes a plurality of the pixel circuits;

the predetermined wiring includes a plurality of vertical signal lines provided for the pixel circuits on a one-to-one basis; and

the third substrate includes a plurality of the circuit elements provided for the vertical signal lines on a one-to-one basis.

17. The solid-state imaging device according to claim 14 , wherein the circuit element includes a conversion circuit configured to convert the pixel signal that has appeared in the predetermined wiring into a digital value.

18. The solid-state imaging device according to claim 17 , wherein the circuit element further includes a logic circuit configured to execute correlated double sampling processing for the pixel signal converted into the digital value by the conversion circuit.

19. The solid-state imaging device according to claim 14 , wherein:

the second substrate includes a plurality of the pixel circuits; and

the drain of the amplification transistor of each of the pixel circuits is connected to the predetermined wiring via the selection transistor.

20. The solid-state imaging device according to claim 19 , wherein

a plurality of the pixel circuits are arranged in a matrix form; and

the drain of the amplification transistor of each of the pixel circuits arranged in the same line among the pixel circuits arranged in the matrix form is connected to the common predetermined wiring via the selection transistor.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 10, 2021
From: TAKIZAWA, MASAAKI; SAKANO, YORITO
To: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
Reel/Frame 057451/0738 →
Priority Claims (1)
JP 2018-174209 · Sep 18, 2018 · national
Continuity (1)
Related Publication 20220037388A1 · Feb 3, 2022