Comparison circuit, and analog-to-digital converter and image sensor including the same
Disclosed is an analog-to-digital converter including a comparison circuit and a counter circuit. The comparison circuit outputs a comparison result signal based on a pixel signal and a ramp signal and outputs a zero-crossing prediction signal, is the comparison circuit being configured to transition the zero-crossing prediction signal before a zero-crossing time point at which a voltage level of the pixel signal becomes identical to a voltage level of the ramp signal and during a time interval during which the voltage level of the ramp signal is reduced. The counter circuit outputs a low-order bit digital code based on the zero-crossing prediction signal and stops the output of the low-order bit digital code based on the comparison result signal.
1. An analog-to-digital converter (ADC) comprising:
a comparison circuit configured to output a comparison result signal based on a pixel signal and a ramp signal and to output a zero-crossing prediction signal, the comparison circuit being configured to transition the zero-crossing prediction signal before a zero-crossing time point at which a voltage level of the pixel signal becomes identical to a voltage level of the ramp signal and during a time interval during which the voltage level of the ramp signal is changed; and
a counter circuit configured to output a low-order bit digital code based on the zero-crossing prediction signal and to stop the output of the low-order bit digital code based on the comparison result signal.
2. The ADC of claim 1 , wherein the comparison circuit includes
a first amplification circuit configured to have a first voltage gain and to generate the comparison result signal, and
a second amplification circuit configured to have a second voltage gain lower than the first voltage gain and to generate the zero-crossing prediction signal.
3. The ADC of claim 2 , wherein the second amplification circuit is connected to a first node included in the first amplification circuit.
4. The ADC of claim 3 , wherein the first amplification circuit includes
a first sub-circuit configured to output a first output signal through the first node by comparing the pixel signal with the ramp signal, and
a second sub-circuit configured to output a second output signal as the comparison result signal by amplifying the first output signal.
5. The ADC of claim 4 , wherein the second amplification circuit includes
a first PMOS transistor and a first NMOS transistor, the first PMOS transistor and the first NMOS transistor being serially connected between a power supply voltage node and a ground voltage node,
a first capacitor connected between the first node and a gate node of the first NMOS transistor, and
a second capacitor connected between the gate node of the first NMOS transistor and a drain node of the first NMOS transistor.
6. The ADC of claim 5 , wherein
the voltage level of the pixel signal becomes substantially identical to the voltage level of the ramp signal during a first time interval,
the voltage level of the ramp signal is increased by an offset voltage during a second time interval,
the voltage level of the ramp signal is decreased with a constant slope during a third time interval, and
the ADC is configured to determine a bias state of each of the first amplification circuit and the second amplification circuit during the first time interval.
7. The ADC of claim 6 , wherein the second amplification circuit further includes a third capacitor connected between the first node and the drain node of the first NMOS transistor.
8. The ADC of claim 7 , wherein
the second capacitor includes a first adjustment capacitor and a second adjustment capacitor,
the first adjustment capacitor and the second adjustment capacitor are serially connected with each other, and
the second amplification circuit further includes a gain adjustment switch connected between the drain node of the first NMOS transistor and a second node, the second node being positioned between the first adjustment capacitor and the second adjustment capacitor.
9. The ADC of claim 8 , wherein the gain adjustment switch is configured to be turned on and turned off based on a gain adjustment control signal.
10. The ADC of claim 7 , wherein
the first sub-circuit includes
a differential circuit configured to receive the pixel signal and the ramp signal,
a current mirror circuit connected between the differential circuit and the power supply voltage node, and
a bias circuit connected between the differential circuit and the ground voltage node,
the current mirror circuit includes
a third PMOS transistor connected between the power supply voltage node and a third node,
a fourth PMOS transistor connected between the third node and a fourth node, and
a fifth PMOS transistor connected between the power supply voltage node and the first node, and
a gate node of the third PMOS transistor is electrically connected to the fourth node and a gate node of the fourth PMOS transistor.
11. The ADC of claim 10 , wherein a voltage level of a source voltage of the fourth PMOS transistor is determined as an overdrive voltage of the third PMOS transistor.
12. The ADC of claim 11 , wherein
the counter circuit includes
a first counter configured to output a high-order bit digital code, and
a second counter configured to output the low-order bit digital code, and
the counter circuit enables the second counter based on the zero-crossing prediction signal and disables the second counter based on the comparison result signal.
13. The ADC of claim 12 , wherein the counter circuit is configured to enable the first counter in response to the voltage level of the ramp signal being decreased with a constant slope, and enable the second counter in response to a voltage level of the zero-crossing prediction signal being increased to be greater than or equal to a first voltage level.
14. The ADC of claim 13 , wherein
the first counter is configured to output the high-order bit digital code in response to the voltage level of the ramp signal being decreased with the constant slope, and is not configured to output the high-order bit digital code in response to a voltage level of the comparison result signal being increased to be greater than or equal to a second voltage level, and
the second counter is configured to output the low-order bit digital code in response to the voltage level of the zero-crossing prediction signal being increased to be greater than or equal to the second voltage level, and is not configured to output the low-order bit digital code in response to the voltage level of the comparison result signal being increased to be greater than or equal to the second voltage level.
15. A comparison circuit comprising:
a first sub-circuit configured to output a first output signal through a first node by comparing a pixel signal with a ramp signal;
a second sub-circuit configured to output a second output signal as a comparison result signal by amplifying the first output signal; and
a zero-crossing prediction circuit configured to output a zero-crossing prediction signal based on the first output signal, is the zero-crossing prediction circuit is configured to transition the zero-crossing prediction signal before a zero-crossing time point at which a voltage level of the pixel signal becomes identical to a voltage level of the ramp signal and during a time interval during which the voltage level of the ramp signal is changed.
16. The comparison circuit of claim 15 , wherein
both the first sub-circuit and the second sub-circuit have a first voltage gain, and
the zero-crossing prediction circuit has a second voltage gain lower than the first voltage gain.
17. The comparison circuit of claim 15 , wherein the zero-crossing prediction circuit includes
a first PMOS transistor and a first NMOS transistor, which are serially connected between a power supply voltage node and a ground voltage node,
a first capacitor connected between the first node and a gate node of the first NMOS transistor, and
a second capacitor connected between the gate node of the first NMOS transistor and a drain node of the first NMOS transistor.
18. The comparison circuit of claim 17 , wherein the zero-crossing prediction circuit further includes a third capacitor connected between the first node and the drain node of the first NMOS transistor.
19. The comparison circuit of claim 18 , wherein
the second capacitor includes a first adjustment capacitor and a second adjustment capacitor,
the first adjustment capacitor and the second adjustment capacitor are serially connected with each other,
the zero-crossing prediction circuit further includes a gain adjustment switch connected between the drain node of the first NMOS transistor and a second node, the second node positioned between the first adjustment capacitor and the second adjustment capacitor, and
the gain adjustment switch configured to be turned on and turned off based on a gain adjustment control signal.
20. A comparison circuit comprising:
a pixel array configured to output a pixel signal;
a ramp signal generator configured to output a ramp signal;
a comparison circuit configured to output a comparison result signal based on the pixel signal and the ramp signal and to output a zero-crossing prediction signal, the comparison circuit is configured to transition the zero-crossing prediction signal before a zero-crossing time point at which a voltage level of the pixel signal becomes identical to a voltage level of the ramp signal and during a time interval during which the voltage level of the ramp signal is changed; and
a counter circuit configured to output a low-order bit digital code based on the zero-crossing prediction signal and to stop the output of the low-order bit digital code based on the comparison result signal,
wherein the comparison circuit includes
a first amplification circuit configured to have a first voltage gain and to generate the comparison result signal; and
a second amplification circuit connected to a first node included in the first amplification circuit and configured to have a second voltage gain lower than the first voltage gain and to generate the zero-crossing prediction signal.