IP Library Granted Patent US 12,096,617
Granted Patent B2
US 12,096,617 · App. 17/650,130 · Granted Sep 17, 2024

Method of manufacturing semiconductor structure and semiconductor structure

Inventors: Er-Xuan Ping (Hefei, CN); Jie Bai (Hefei, CN); Juanjuan Huang (Hefei, CN)
Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
H10B12/482H10B12/30
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Quick Facts
Patent No.
US 12,096,617
App. No.
17/650,130
Granted
Sep 17, 2024
Kind
B2
Abstract

A method of manufacturing a semiconductor structure and a semiconductor structure are disclosed in embodiments of the present disclosure. The method of manufacturing a semiconductor includes: providing a base; and forming an electrical contact layer, a bottom barrier layer, and a conductive layer that are sequentially stacked on the base, where a material of the conductive layer includes molybdenum.

Claims (26)

1. A semiconductor structure, comprising:

a base;

an electrical contact layer located on the base;

a bottom barrier layer located on the electrical contact layer; and

a conductive layer located on the bottom barrier layer; and,

wherein a material of the conductive layer comprises molybdenum, the conductive layer is a multi-layer structure, the conductive layer comprises a contact region in contact with the bottom barrier layer and a connection region located on the contact region, a material of the contact region comprises molybdenum, and an etching rate of the connection region is higher than an etching rate of the contact region under a same etching condition.

2. The semiconductor structure according to claim 1 , wherein a material of the connection region comprises tungsten, and a thickness ratio between the contact region and the connection region ranges from 2:1 to 3:1 in a direction perpendicular to a top surface of the base.

3. The semiconductor structure according to claim 1 , wherein the semiconductor structure further comprising: a top barrier layer located on the conductive layer.

4. The semiconductor structure according to claim 3 , wherein a thickness of the bottom barrier layer is greater than a thickness of the top barrier layer in a direction perpendicular to a top surface of the base.

5. The semiconductor structure according to claim 4 , wherein the thickness of the bottom barrier layer ranges from 1 nm to 5 nm in the direction perpendicular to the top surface of the base; the thickness of the top barrier layer ranges from 0.1 nm to 1 nm in the direction perpendicular to the top surface of the base.

6. The semiconductor structure according to claim 1 , wherein the semiconductor structure further comprising: a sidewall barrier layer located on sidewalls of the conductive layer.

7. The semiconductor structure according to claim 6 , wherein the sidewall barrier layer has a thickness of 0.1 nm to 1 nm in a direction parallel to a top surface of the base.

8. The semiconductor structure according to claim 1 , wherein the conductive layer has a thickness of 20 nm to 40 nm in a direction perpendicular to a top surface of the base.

9. The semiconductor structure according to claim 1 , wherein a material of the bottom barrier layer comprises molybdenum nitride.

10. A method of manufacturing a semiconductor structure according to claim 1 , comprising:

providing a base; and

forming an electrical contact layer, a bottom barrier layer, and a conductive layer that are sequentially stacked on the base;

wherein a material of the conductive layer comprises molybdenum, the conductive layer is a multi-layer structure, the conductive layer comprises a contact region in contact with the bottom barrier layer and a connection region located on the contact region, a material of the contact region comprises molybdenum, and an etching rate of the connection region is higher than an etching rate of the contact region under a same etching condition.

11. The method of manufacturing the semiconductor structure according to claim 10 , wherein a material of the connection region comprises tungsten.

12. The method of manufacturing the semiconductor structure according to claim 10 , wherein a thickness ratio between the contact region and the connection region ranges from 2:1 to 3:1 in a direction perpendicular to a top surface of the base.

13. The method of manufacturing the semiconductor structure according to claim 10 , wherein a method for forming the electrical contact layer, the conductive layer, and the bottom barrier layer comprises: forming an initial electrical contact layer on the base, and forming an initial bottom barrier layer on the initial electrical contact layer; forming an initial conductive layer on the initial bottom barrier layer; and patterning the initial electrical contact layer, the initial bottom barrier layer, and the initial conductive layer, and forming the electrical contact layer, the conductive layer, and the bottom barrier layer.

14. The method of manufacturing the semiconductor structure according to claim 13 , wherein the initial conductive layer is patterned by using a dry etching method, and an etching gas is chlorine, with a flow rate of 10 sccm to 40 sccm, in a process of etching the initial conductive layer.

15. The method of manufacturing the semiconductor structure according to claim 13 , wherein after forming the initial conductive layer, the method further comprising: forming an initial top barrier layer on the initial conductive layer; and

patterning the initial top barrier layer, and forming a top barrier layer.

16. The method of manufacturing the semiconductor structure according to claim 15 , wherein the forming the initial top barrier layer on the initial conductive layer comprises: processing the initial conductive layer by using a remote plasma nitridation process to form the initial top barrier layer.

17. The method of manufacturing the semiconductor structure according to claim 10 , wherein after forming the conductive layer, the method further comprising: forming a sidewall barrier layer on sidewalls of the conductive layer by using a remote plasma nitridation process.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 7, 2022
From: PING, ER-XUAN; BAI, JIE; HUANG, JUANJUAN
To: CHANGXIN MEMORY TECHNOLOGIES, INC.
Reel/Frame 058909/0343 →
Priority Claims (1)
CN 202110050700.1 · Jan 14, 2021 · national
Continuity (2)
Continuation PCTCN2021111383 · Aug 9, 2021
Related Publication 20220223603A1 · Jul 14, 2022