Array substrate and manufacturing method thereof, and display panel

1. An array substrate, comprising:

a substrate;

a first active layer of a first thin film transistor, wherein the first active layer comprises a channel region, a source contact region and a drain contact region, wherein the source contact region and the drain contact region are positioned on two sides of the channel region;

a first insulating layer on the first active layer;

a first metal layer on the first insulating layer, wherein the first metal layer comprises a first connection portion, and the first connection portion overlaps one of the source contact region or the drain contact region of the first active layer;

an auxiliary conductive layer located below the first active layer, and an auxiliary connection portion electrically connected to the auxiliary conductive layer, wherein the auxiliary connection portion and the first connection portion are arranged in a same layer and made of a same material; and

a second active layer of a second thin film transistor, wherein the second active layer is on the first insulating layer and the first connection portion, and comprises a channel region, a source contact region and a drain contact region, wherein the source contact region and the drain contact region are positioned on two sides of the channel region, and the first connection portion overlaps one of the source contact region or the drain contact region of the second active layer,

wherein the one of the source contact region or the drain contact region of the first active layer and the one of the source contact region or the drain contact region of the second active layer overlap, and are electrically connected to each other through the first connection portion and a via in the first insulating layer.

2. The array substrate of claim 1 , wherein the first active layer is a low temperature poly silicon, and the second active layer is an oxide semiconductor.

3. The array substrate of claim 1 , wherein the first thin film transistor further comprises a first gate electrode overlapping the channel region of the first active layer, wherein the first gate electrode and the first connection portion are insulated from each other, arranged in a same layer and made of a same material.

4. The array substrate of claim 1 , further comprising: a capacitor electrode located on the first insulating layer, wherein the capacitor electrode and the first connection portion are insulated from each other, arranged in a same layer and made of a same material.

5. The array substrate of claim 1 , wherein the first metal layer further comprises a second connection portion, and the second connection portion overlaps at least one of the source contact region or the drain contact region of the first active layer, and is electrically connected to the one of the source contact region or the drain contact region of the first active layer through a via in the first insulating layer,

wherein a first one of the first connection portion and the second connection portion is connected to the drain contact region of the first active layer, and a second one of the first connection portion and the second connection portion is connected to the source contact region of the first active layer.

6. The array substrate of claim 1 , wherein the auxiliary conductive layer overlaps the first active layer and is multiplexed as a gate electrode of the first thin film transistor.

7. The array substrate of claim 1 , wherein the first thin film transistor further comprises a first gate electrode located above the first active layer and an auxiliary gate electrode located bellow the first active layer,

wherein the first gate electrode and the first connection portion are insulated from each other, but are arranged in a same layer and made of a same material; the auxiliary connection portion is at least partially multiplexed as the first gate electrode; and at least part of the auxiliary conductive layer is multiplexed as the auxiliary gate electrode.

8. The array substrate of claim 1 , wherein the auxiliary connection portion is multiplexed as the first connection portion.

9. The array substrate of claim 1 , wherein the auxiliary conductive layer is made of a light-shielding material.

10. The array substrate of claim 1 , wherein gate and drain electrodes of the first thin film transistor are electrically connected through the auxiliary connection portion; or gate and source electrodes of the first thin film transistor are electrically connected through the auxiliary connection portion.

11. The array substrate of claim 1 , further comprising:

a second insulating layer, located on the second active layer; and

a second metal layer, located on the second insulating layer,

wherein the second metal layer comprises a second source electrode and a second drain electrode overlapping at least one of the source contact region or the drain contact region of the second active layer, and wherein the second source electrode is electrically connected the source contact region of the second active layer through a via in the second insulating layer and the second drain electrode is electrically connected the drain contact region of the second active layer through another via in the second insulating layer,

wherein one of the second source electrode and the second drain electrode overlaps the first connection portion, and is electrically connected to the first connection portion through a via in the one of the source contact region or the drain contact region.

12. The array substrate of claim 11 , wherein

the second metal layer further comprises a first source electrode and a first drain electrode overlapping at least one of the source contact region or the drain contact region of the first active layer, and wherein the first source electrode is electrically connected to the source contact region of the first active layer through a via in the second insulating layer, and the first drain electrode is electrically connected to the drain contact region of the first active layer through another via in the second insulating layer.

13. A display panel, comprising: an array substrate, wherein the array substrate comprises:

a substrate;

a first active layer a first thin film transistor, wherein the first active layer is on the substrate, and comprises a channel region, a source contact region and a drain contact region, wherein the source contact region and the drain contact region are positioned on two sides of the channel region;

a first insulating layer on the first active layer;

a first metal layer on the first insulating layer, wherein the first metal layer comprises a first connection portion, and the first connection portion overlaps one of the source contact region or the drain contact region of the first active layer;

an auxiliary conductive layer located below the first active layer, and an auxiliary connection portion electrically connected to the auxiliary conductive layer, wherein the auxiliary connection portion and the first connection portion are arranged in a same layer and made of a same material; and

a second active layer a second thin film transistor, wherein the second active layer is on the first insulating layer and the first connection portion, and comprises a channel region, a source contact region and a drain contact region, wherein the source contact region and the drain contact region are positioned on two sides of the channel region, and the first connection portion overlaps one of the source contact region or the drain contact region of the second active layer,

wherein the one of the source contact region or the drain contact region of the first active layer and the one of the source contact region or the drain contact region of the second active layer overlap, and are electrically connected to each other through the first connection portion and a via in the first insulating layer.

14. A manufacturing method of an array substrate, comprising:

providing a substrate;

forming a first active layer of a first thin film transistor on one side of the substrate, wherein the first active layer comprises a channel region, and a source contact region and a drain contact region located on two sides of the channel region;

forming a first insulating layer on one side, facing away from the substrate, of the first active layer, and forming a first via in the first insulating layer, wherein one of the source contact region or the drain contact region of the first active layer is exposed by the first via;

forming a first metal layer on one side, facing away from the substrate, of the first insulating layer;

patterning the first metal layer to at least form a first connection portion and an auxiliary conductive layer, wherein the first connection portion overlaps one of the source contact region or the drain contact region of the first active layer, and contacts the one of the source contact region or the drain contact region of the first active layer through the first via; and wherein the auxiliary conductive layer is located below the first active layer, an auxiliary connection portion electrically is connected to the auxiliary conductive layer, and the auxiliary connection portion and the first connection portion are arranged in a same layer and made of a same material; and

forming, on one side of the first metal layer facing away from the substrate, a second active layer of a second thin film transistor, wherein the second active layer comprises a channel region, and a source contact region and a drain contact region located on two sides of the channel region, and the first connection portion overlaps one of the source contact region or the drain contact region of the second active layer.

15. The manufacturing method of claim 14 , wherein patterning the first metal layer further comprises one or more of: forming a gate electrode of the first thin film transistor and forming a capacitor electrode.

16. The manufacturing method of claim 14 , further comprising:

forming a second insulating layer on one side, facing away from the substrate, of the second active layer, and forming, in the second insulating layer, a second via exposing one of the source contact region or the drain contact region of the second active layer;

forming a second metal layer on one side, facing away from the substrate, of the second insulating layer; and

patterning the second metal layer to at least form a second source electrode and a second drain electrode overlapping at least one of the source contact region or the drain contact region of the second active layer, wherein one of the second source electrode and the second drain electrode is electrically connected to the one of the source contact region or the drain contact region of the second active layer through the second via.

17. The manufacturing method of claim 16 , wherein after forming the second via, the method further comprises forming, in the second active layer which is exposed through the second via, a fifth via exposing the first connection portion; and

after forming the second source electrode and the second drain electrode, one of the second source electrode and the second drain electrode contacts and is connected to the first connection portion through the second via and the fifth via.

18. The manufacturing method of claim 14 , wherein after forming the first insulating layer on the one side, facing away from the substrate, of the first active layer, the method comprises forming, in the first insulating layer, a third via exposing the one of the source contact region or the drain contact region of the first active layer; and

wherein patterning the first metal layer further comprises forming a second connection portion, wherein the second connection portion overlaps at least one of the source contact region or the drain contact region of the first active layer, and is electrically connected to the one of the source contact region or the drain contact region of the first active layer through the third via.

19. The manufacturing method of claim 18 , wherein the first active layer is a low temperature poly silicon, and the second active layer is an oxide semiconductor; and

before forming the first metal layer, the method comprises processing the first active layer with hydrofluoric acid.