Semiconductor device and method of manufacturing same

1. A method of fabricating a semiconductor device, the method comprising:

forming a semiconductor substrate having a first protected circuit; and

forming a first guard ring; and

forming a second guard ring adjacent to the first guard ring and around the first protected circuit including:

forming a first wall configured to provide a first reference voltage;

forming a second wall configured to provide a second reference voltage different than the first reference voltage; and

forming at least a third wall configured to provide the first reference voltage.

2. The method of claim 1 , further comprising:

forming a buried power grid (BPG) beneath the semiconductor substrate; and

wherein the forming a second guard ring further includes:

incorporating a portion of the BPG into the second guard ring.

3. The method of claim 2 , wherein:

the second guard ring is formed on a first side of the semiconductor substrate, and

the forming a BPG beneath the semiconductor substrate includes:

forming the BPG on a second side of the semiconductor substrate opposite the first side.

4. The method of claim 2 , wherein:

the portion of the BPG includes at least one conductor provided in at least one via tower or in at least one via-bar tower.

5. The method of claim 1 , further comprising:

forming a non-buried power grid (non-BPG) above the semiconductor substrate; and

wherein the forming a second guard ring further includes:

incorporating a portion of the non-BPG into the second guard ring.

6. The method of claim 5 , wherein:

the portion of the non-BPG includes at least one conductor in at least one via tower or in at least one via-bar tower.

7. The method of claim 1 , further comprising:

forming a second protected circuit; and

wherein:

the forming a second guard ring further includes:

disposing the second guard ring around the second protected circuit;

the first protected circuit is a transistor driver array; and

the second protected circuit is an array of electrostatic discharge clamp circuits.

8. A method of operating a semiconductor device which includes a first guard ring, a second guard ring adjacent to the first guard ring and around a first protected circuit, the second guard ring including a first wall, a second wall, and a third wall, the method comprising;

biasing the first wall of the second guard ring with a first reference voltage;

biasing the second wall of the second guard ring with a second reference voltage different than the first reference voltage; and

biasing the third wall of the second guard ring with the first reference voltage.

9. The method of claim 8 , wherein:

the semiconductor device further includes a buried power grid (BPG) beneath a semiconductor substrate; and

at least one of the following is true:

the biasing the first wall includes:

electrically coupling a first portion of the BPG to the first wall; or

the biasing the second wall includes:

 electrically coupling a second portion of the BPG to the second wall.

10. The method of claim 9 , wherein:

the second guard ring is on a first side of a semiconductor substrate,

the BPG is on a second side of the semiconductor substrate, and

at least one of the following is true:

the biasing the first wall includes:

electrically coupling a first portion of the BPG on the second side of the semiconductor substrate to the first wall on the first side of the semiconductor substrate; or

the biasing the second wall includes:

electrically coupling a second portion of the BPG on the second side of the semiconductor substrate to the second wall on the first side of the semiconductor substrate.

11. The method of claim 9 , wherein:

the first portion of the BPG includes at least one conductor provided in at least one via tower or in at least one via-bar tower; or

the second portion of the BPG includes at least one conductor provided in at least one via tower or in at least one via-bar tower.

12. The method of claim 8 , wherein:

the semiconductor device further includes a non-buried power grid (non-BPG) above a semiconductor substrate; and

at least one of the following is true:

the biasing the first wall includes:

electrically coupling a first portion of the non-BPG to the first wall; or

the biasing the second wall includes:

electrically coupling a second portion of the non-BPG to the second wall.

13. The method of claim 12 , wherein:

the first portion of the non-BPG includes at least one conductor in at least one via tower or in at least one via-bar tower; or

the second portion of the non-BPG includes at least one conductor in at least one via tower or in at least one via-bar tower.

14. A semiconductor device, comprising:

a semiconductor substrate having a first protected circuit;

a first guard ring; and

a second guard ring adjacent to the first guard ring and around the first protected circuit, the second guard ring including:

a first wall configured to provide a first reference voltage;

a second wall configured to provide a second reference voltage different than the first reference voltage; and

at least a third wall configured to provide the first reference voltage.

15. The semiconductor device of claim 14 , further comprising:

a buried power grid (BPG) beneath the semiconductor substrate; and

wherein the second guard ring includes at least a portion of the BPG.

16. The semiconductor device of claim 15 , wherein:

the second guard ring is on a first side of a semiconductor substrate, and

the BPG is on a second side of the semiconductor substrate opposite the first side.

17. The semiconductor device of claim 15 , wherein:

the at least the portion of the BPG includes at least one conductor provided in at least one via tower or at least one via-bar tower.

18. The semiconductor device of claim 15 , further comprising:

a non-buried power grid (non-BPG) above the semiconductor substrate; and

wherein the second guard ring includes at least a portion of the non-BPG.

19. The semiconductor device of claim 18 , wherein the at least the portion of the non-BPG includes at least one conductor in at least one via tower or at least one via-bar tower.

20. The semiconductor device of claim 14 , further comprising:

a second protected circuit; and

wherein:

the second guard ring is around the second protected circuit;

the first protected circuit is a transistor driver array; and

the second protected circuit is an array of electrostatic discharge clamp circuits.