Lateral double-diffused transistor and manufacturing method thereof
The present disclosure relates to a lateral double-diffused transistor and a manufacturing method of the transistor. The transistor comprises: a substrate; a well region and a drift region both located in the top of the substrate, a source region located in the well region, and a drain region located in the drift region; a first dielectric layer located on a surface of the drift region; a first field plate layer located above the drift region and covering a first portion of the first dielectric layer; a second dielectric layer covering a surface of part of the first field plate layer and stacked on a surface of a second portion of the first dielectric layer; a second field plate layer located on a surface of the second dielectric layer, comprising at least one contact channel. According to the present disclosure, the transistor increases breakdown voltage and reduces on-state resistance.
1. A lateral double-diffused transistor, wherein the transistor comprises:
a substrate;
a well region and a drift region both located in top of the substrate, a source region located in the well region, and a drain region located in the drift region;
a first dielectric layer located on a surface of the drift region;
a first field plate layer located above the drift region and covering a first portion of the first dielectric layer;
a second dielectric layer covering a surface of part of the first field plate layer and stacked on a surface of a second portion of the first dielectric layer;
a second field plate layer located on a surface of the second dielectric layer, wherein the second field plate layer comprising at least one contact channel,
wherein an oxide layer is directly located on an upper surface of the second dielectric layer, each of the at least one contact channel extends from an upper surface of the oxide layer to an upper surface of a portion of the second dielectric layer, wherein the portion of the second dielectric layer has a lower surface in direct contact with the second portion of the first dielectric layer or in direct contact with the surface of part of the first field plate layer,
wherein each contact channel included in the at least one contact channel is a metal plug filled in a corresponding one of at least one through hole which is formed in the second field plate layer and extends perpendicularly to the surface of the second dielectric layer.
2. The lateral double-diffused transistor according to claim 1 , wherein the second dielectric layer is a salicidation block layer which prevents metal silicide from forming in a region covered by the salicidation block layer.
3. The lateral double-diffused transistor according to claim 2 , wherein the salicidation block layer is an oxide layer.
4. The lateral double-diffused transistor according to claim 1 , wherein the second field plate layer comprises a plurality of contact channels, each of which is included in said at least one contact channel, arranged in a row along an extension direction from the source region to the drain region.
5. The lateral double-diffused transistor according to claim 4 , wherein one of the plurality of contact channels which is located above the first field plate layer has a height less than a height of another one of the plurality of contact channels which is located above the second portion of the first dielectric layer.
6. The lateral double-diffused transistor according to claim 4 , wherein the plurality of contact channels are respectively connected to different potentials.
7. The lateral double-diffused transistor according to claim 1 , wherein the transistor further comprises:
a side wall which is located in a contact region between a side surface of the first field plate layer and the second dielectric layer, and used as an isolation layer.
8. The lateral double-diffused transistor according to claim 1 , wherein the first dielectric layer extends along a direction from the source region to the drain region and covers a part of the drain region.
9. A manufacturing method of a lateral double-diffused transistor, comprising:
forming a well region and a drift region in top of substrate;
forming a source region located in the well region, and a drain region located in the drift region;
forming a first dielectric layer located on a surface of the drift region;
forming a first field plate layer located above the drift region and covering a surface of a first portion of the first dielectric layer;
forming a second dielectric layer covering a surface of a part of the first field plate layer and stacked on a surface of a second portion of the first dielectric layer;
forming a second field plate layer located on a surface of the second dielectric layer, wherein the second field plate layer comprising at least one contact channel,
wherein an oxide layer is directly located on an upper surface of the second dielectric layer, each of the at least one contact channel extends from an upper surface of the oxide layer to an upper surface of a portion of the second dielectric layer, wherein the portion of the second dielectric layer has a lower surface in direct contact with the second portion of the first dielectric layer or in direct contact with the surface of part of the first field plate layer,
wherein each contact channel included in the at least one contact channel is a metal plug filled in a corresponding one of at least one through hole which is formed in the second field plate layer and extends perpendicularly to the surface of the second dielectric layer.
10. The manufacturing method according to claim 9 , wherein the second dielectric layer is a salicidation block layer which prevents metal silicide from forming in a region covered by the salicidation block layer.
11. The manufacturing method according to claim 10 , wherein the salicidation block layer is an oxide layer.
12. The manufacturing method according to claim 9 , wherein the second field plate layer comprises a plurality of contact channels, each of which is included in said at least one contact channel, arranged in a row along an extension direction from the source region to the drain region.
13. The manufacturing method according to claim 12 , wherein one of the plurality of contact channels which is located above the first field plate layer has a height less than another one of the plurality of contact channels which is located above the second portion of the first dielectric layer.
14. The manufacturing method according to claim 12 , wherein the plurality of contact channels are respectively connected to different potentials.
15. The manufacturing method according to claim 9 , further comprising:
forming a side wall located in a contact region between a side surface of the first field plate layer and the second dielectric layer.
16. The manufacturing method according to claim 9 , wherein step of forming the second dielectric layer comprises:
depositing the salicidation block layer on the surface of the substrate, the first field plate layer, and the first dielectric layer;
covering a surface of the salicidation block layer located above the drift region with a resist mask; and
etching and removing a portion of the salicidation block layer which is uncovered by the resist mask.
17. The manufacturing method according to claim 11 , wherein step of forming the second field plate layer comprises:
successively depositing an oxide layer, an etching barrier layer and an interlayer dielectric layer on the surface of the second dielectric layer;
etching the interlayer dielectric layer, the etching barrier layer and the oxide layer to form the at least one through hole;
depositing metal in each one of the at least one through hole to form the corresponding metal plug; and
performing planarization.
18. The manufacturing method according to claim 9 , wherein material of the first field plate layer comprises polysilicon, and material of the first dielectric layer comprises oxide.
19. The manufacturing method according to claim 9 , wherein a thickness of the first dielectric layer is 300-800 angstroms, and a thickness of the second dielectric layer is 500-1000 angstroms.