IP Library › Granted Patent US 12,101,067
Granted Patent B2
US 12,101,067 · App. 17/614,690 · Granted Sep 24, 2024

Semiconductor device

Inventors: Minato Ito (Kanagawa, JP); Hitoshi Kunitake (Kanagawa, JP); Takayuki Ikeda (Kanagawa, JP)
Assignee: Semiconductor Energy Laboratory Co., Ltd.
H03F3/45475H01L27/1225H01L27/1255H01L29/78648H01L29/7869H10B12/00H03F2203/45594
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Quick Facts
Patent No.
US 12,101,067
App. No.
17/614,690
Granted
Sep 24, 2024
Kind
B2
Abstract

A semiconductor device that functions as a relay station and is reduced in size is provided. The semiconductor device includes an operational amplifier, a first transistor and a first capacitor that are electrically connected to a first input side of the operational amplifier, and a first resistor and a second resistor that are electrically connected to a second input side. The second resistor is electrically connected to an output side of the operational amplifier, a gate of the first transistor is electrically connected to a first power supply, the first resistor is electrically connected to a second power supply, and at least a transistor included in the operational amplifier has a region overlapping with the first transistor.

Claims (39)

1. A semiconductor device comprising:

an operational amplifier between an input terminal of a phase shifter and an output terminal of the phase shifter;

a transistor electrically connected to a first input terminal of the operational amplifier;

a first resistor electrically connected to a second input terminal of the operational amplifier; and

a second resistor electrically connected to the second input terminal of the operational amplifier,

wherein a gate of the transistor is electrically connected to a first terminal,

wherein one of a source and a drain of the transistor is electrically connected to the input terminal of the phase shifter,

wherein the other of the source and the drain of the transistor is electrically connected to the first input terminal of the operational amplifier,

wherein the first resistor is electrically connected to the input terminal of the phase shifter,

wherein the second resistor is electrically connected to the output terminal of the phase shifter, and

wherein at least a transistor included in the operational amplifier comprises a region overlapping with the transistor.

2. A semiconductor device comprising:

an operational amplifier between an input terminal of a phase shifter and an output terminal of the phase shifter;

a transistor electrically connected to a first input terminal of the operational amplifier;

a capacitor electrically connected to one of a source and a drain of the transistor;

a first resistor electrically connected to a second input terminal of the operational amplifier; and

a second resistor electrically connected to the second input terminal of the operational amplifier,

wherein a gate of the transistor is electrically connected to a first terminal,

wherein the other of the source and the drain of the transistor is electrically connected to the input terminal of the phase shifter,

wherein the one of the source and the drain of the transistor is electrically connected to the first input terminal of the operational amplifier,

wherein the first resistor is electrically connected to the input terminal of the phase shifter,

wherein the second resistor is electrically connected to the output terminal of the phase shifter, and

wherein at least a transistor included in the operational amplifier comprises a region overlapping with the transistor.

3. A semiconductor device comprising:

an operational amplifier between an input terminal of a phase shifter and an output terminal of the phase shifter;

a transistor electrically connected to a first input terminal of the operational amplifier;

a memory element electrically connected to a gate of the transistor;

a first resistor electrically connected to a second input terminal of the operational amplifier; and

a second resistor electrically connected to the second input terminal of the operational amplifier,

wherein the gate of the transistor is electrically connected to a first terminal,

wherein one of a source and a drain of the transistor is electrically connected to the input terminal of the phase shifter,

wherein the other of the source and the drain of the transistor is electrically connected to the first input terminal of the operational amplifier,

wherein the first resistor is electrically connected to the input terminal of the phase shifter,

wherein the second resistor is electrically connected to the output terminal of the phase shifter, and

wherein at least a transistor included in the operational amplifier comprises a region overlapping with the transistor.

4. The semiconductor device according to claim 3 ,

wherein the memory element comprises a first transistor and a first capacitor,

wherein the first transistor comprises an oxide semiconductor film, and

wherein at least the transistor included in the operational amplifier comprises a region overlapping with the first transistor.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 29, 2021
From: ITO, MINATO; KUNITAKE, HITOSHI; IKEDA, TAKAYUKI
To: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
Reel/Frame 058227/0753 →
Priority Claims (1)
JP 2019-106670 · Jun 7, 2019 · national
Continuity (1)
Related Publication 20220231644A1 · Jul 21, 2022