Fractional divider with duty cycle regulation and low subharmonic content
View Patent ↗Systems, devices, and methods related to frequency divider circuitry are provided. An apparatus includes frequency divider circuitry including a first node to receive an input signal; fractional divider circuitry to generate, based on the input signal and a frequency-division ratio, a first signal having a first series of pulses with adjacent pulses triggered by opposite edges of the input signal, wherein the fractional divider circuitry includes first signal selection circuitry; balancer divider circuitry to generate, based on the input signal, a second signal having a second series of pulses aligned to the first series of pulses, wherein the balancer divider circuitry includes second signal selection circuitry triggered by opposite edges of the input signal than the first signal selection circuitry; and a second node to combine the first signal and the second signal.
1. A device, comprising:
duty cycle correction circuitry configured to generate, based on an input signal, an output signal having a target duty cycle, the duty cycle correction circuitry comprising:
first circuitry configured to generate a rising edge of the output signal from a rising edge of the input signal, and further configured to generate a falling edge of the output signal based on a feedback signal representative of duty cycle information of the output signal, the first circuitry comprising a first inverter configured to receive the input signal and a second inverter configured to receive the feedback signal.
2. The device of claim 1 , wherein the first circuitry further comprises a set-reset latch including a first NAND gate and a second NAND gate, and wherein the first NAND gate is coupled with the first inverter and the second NAND gate is coupled with the second inverter.
3. The device of claim 2 , wherein the duty cycle correction circuitry further comprises second circuitry including:
a filter configured to output a direct current (DC) component of the output signal;
an amplifier device including:
a first input configured to receive the DC component;
a second input configured to receive a reference voltage; and
an output configured to supply an error signal corresponding to a difference between the DC component and the reference voltage; and
a variable delay line controlled by the error signal to generate the feedback signal.
4. The device of claim 3 , wherein the reference voltage determines the target duty cycle.
5. The device of claim 3 , wherein the reference voltage is half of a supply voltage and causes the target duty cycle to be 50% of a duty cycle of the input signal.
6. The device of claim 3 , wherein to generate the falling edge of the output signal based on the feedback signal the first circuitry is further configured to generate the falling edge of the output signal from a rising edge of the feedback signal.
7. The device of claim 6 , further comprising third circuitry configured to generate the input signal according to a frequency-division ratio, wherein adjacent pulses in the input signal are triggered by opposite edges of a reference signal, resulting in the input signal having a frequency that is equal to a second frequency of the reference signal multiplied by the frequency-division ratio.
8. The device of claim 7 , wherein the frequency-division ratio is equal to 1.5.
9. A device, comprising:
a pulse generator configured to,
receive an input signal;
generate a rising edge of an output signal from a rising edge of the input signal; and
generate a falling edge of the output signal based on a feedback signal representative of duty cycle information of the output signal,
wherein the output signal has a target duty cycle.
10. The device of claim 9 , wherein the pulse generator comprises:
a set-reset latch including a first NAND gate and a second NAND gate;
a first inverter coupled with the first NAND gate and configured to receive the input signal; and
a second inverter coupled with the second NAND gate and configured to receive the feedback signal.
11. The device of claim 10 , further comprising a delay-locked loop (DLL) coupled with the pulse generator, the DLL including:
a filter configured to output a direct current (DC) component of the output signal;
an amplifier device including:
a first input configured to receive the DC component;
a second input configured to receive a reference voltage; and
an output configured to supply an error signal corresponding to a difference between the DC component and the reference voltage; and
a variable delay line controlled by the error signal to generate the feedback signal.
12. The device of claim 11 , wherein the reference voltage determines the target duty cycle.
13. The device of claim 11 , wherein the reference voltage is half of a supply voltage and causes the target duty cycle to be 50% of a duty cycle of the input signal.
14. The device of claim 11 , wherein to generate the falling edge of the output signal based on the feedback signal the pulse generator is further configured to generate the falling edge of the output signal from a rising edge of the feedback signal.
15. The device of claim 14 , further comprising circuitry configured to generate the input signal according to a frequency-division ratio, wherein adjacent pulses in the input signal are triggered by opposite edges of a reference signal, resulting in the input signal having a frequency that is equal to a second frequency of the reference signal multiplied by the frequency-division ratio.
16. The device of claim 15 , wherein the frequency-division ratio is equal to 1.5.
17. A method, comprising:
receiving, by pulse generator circuitry, an input signal; and
generating, by the pulse generator circuitry, based on the input signal, an output signal having a target duty cycle, wherein the generating comprises:
generating a rising edge of the output signal from a rising edge of the input signal; and
generating a falling edge of the output signal based on a feedback signal representative of duty cycle information of the output signal.
18. The method of claim 17 , wherein the pulse generator circuitry comprises:
a set-reset latch including a first NAND gate and a second NAND gate;
a first inverter coupled with the first NAND gate and configured to receive the input signal; and
a second inverter coupled with the second NAND gate and configured to receive the feedback signal.
19. The method of claim 18 , further comprising:
outputting, by a filter of a delay-locked loop (DLL) coupled with the pulse generator circuitry, a direct current (DC) component of the output signal;
receiving, by an amplifier of the DLL, the DC component;
receiving, by the amplifier, a reference voltage;
supplying, by the amplifier, an error signal corresponding to a difference between the DC component and the reference voltage; and
generating, by a variable delay line of the DLL, using the error signal, the feedback signal.
20. The method of claim 19 , wherein the reference voltage is half of a supply voltage and causes the target duty cycle to be 50% of a duty cycle of the input signal.