System and method for constant transconductance based power supply detection
View Patent ↗In some aspects of the present disclosure, a power detection system is disclosed. In some aspects, the power detection system includes a constant-transconductance (gm) reference generator circuit receiving a power supply voltage. In some embodiments, the constant-gm reference generator circuit includes a first current mirror to provide a first reference voltage and a second current mirror to provide a second reference voltage. In some embodiments, the constant-gm reference generator circuit includes a power detection circuit coupled to the first current mirror to receive the first reference voltage. In some embodiments, the power detection circuit is coupled to the second current mirror to receive the second reference voltage. In some embodiments, the power detection is operated to receive the power supply voltage. In some embodiments, the power detection circuit is operated to provide an output voltage having one of two logic states at least based on the second reference voltage and the power supply voltage.
1. A power detection system comprising:
a constant-transconductance (gm) reference generator circuit receiving a power supply voltage, wherein the constant-gm reference generator circuit comprises a first current mirror to provide a first reference voltage and a second current mirror to provide a second reference voltage;
a power detection circuit coupled to the first current mirror to receive the first reference voltage, wherein the power detection circuit is coupled to the second current mirror to receive the second reference voltage, wherein the power detection circuit is operated to receive the power supply voltage, wherein the power detection circuit is operated to provide an output voltage having one of two logic states at least based on the second reference voltage and the power supply voltage; and
a second power detection circuit, wherein the constant-gm reference generator circuit further comprises a third current mirror, wherein the second power detection circuit is coupled to the first current mirror to receive the first reference voltage, wherein the second power detection circuit is coupled to the third current mirror to receive a third reference voltage, wherein the second power detection circuit receives a second power supply voltage, wherein the second power detection circuit provides a second output voltage having one of two logic states at least based on third reference voltage and the second power supply voltage.
2. The power detection system of claim 1 , wherein the power detection circuit comprises an N-type metal-oxide-semiconductor (NMOS) transistor and a P-type metal-oxide-semiconductor (PMOS) transistor coupled to the NMOS transistor, wherein the NMOS transistor is coupled to the first current mirror and the PMOS transistor is coupled to the second current mirror.
3. The power detection system of claim 1 , wherein the power detection circuit comprises a comparator and a current source, wherein the current source is coupled to the first current mirror and the comparator is coupled to the second current mirror.
4. The power detection system of claim 3 , wherein the comparator receives the power supply voltage.
5. The power detection system of claim 3 , wherein the power detection circuit comprises a voltage divider receiving the power supply voltage, and the comparator is coupled to an output port of the voltage divider.
6. The power detection system of claim 1 , further comprising a second power detection circuit, wherein the constant-gm reference generator circuit further comprises a third current mirror, wherein the second power detection circuit is coupled to the first current mirror to receive the first reference voltage, wherein the second power detection circuit is coupled to the third current mirror to receive a third reference voltage, wherein the second power detection circuit receives a second power supply voltage, wherein the second power detection circuit provides a second output voltage having one of two logic states at least based on third reference voltage and the second power supply voltage.
7. The power detection system of claim 1 , wherein a magnitude of the second power supply voltage is less than a magnitude of the power supply voltage.
8. The power detection system of claim 1 , wherein the second power detection circuit comprises an N-type metal-oxide-semiconductor (NMOS) transistor and a P-type metal-oxide-semiconductor (PMOS) transistor coupled to the NMOS transistor, wherein the NMOS transistor is coupled to the first current mirror and the PMOS transistor is coupled to the third current mirror.
9. The power detection system of claim 1 , wherein the second power detection circuit comprises a second comparator and a second current source, wherein the second current source is coupled to the first current mirror and the second comparator is coupled to the third current mirror.
10. The power detection system of claim 9 , wherein the second power detection circuit comprises a voltage divider receiving the power supply voltage, and the second comparator is coupled to the voltage divider.
11. The power detection system of claim 1 , further comprising an output stage coupled to the power detection circuit to receive the output voltage from the power detection circuit and provide a power ready voltage.
12. The power detection system of claim 11 , wherein the output stage comprises a first inverter and a second inverter coupled to the first inverter.
13. The power detection system of claim 11 , wherein the output stage comprises a NAND gate and an inverter coupled to the NAND gate.
14. The power detection system of claim 1 , wherein the power detection system consumes less than a 1 uA of direct current.
15. The power detection system of claim 14 , wherein the constant-gm reference generator circuit comprises a diode-connected P-type metal-oxide-semiconductor (PMOS) transistor and a current-mirror PMOS transistor coupled to the diode-connected PMOS transistor, wherein a ratio of the current-mirror PMOS to the diode-connected PMOS is less than four.
16. A method for power detection comprising:
receiving a reference voltage from a constant-transconductance (gm) reference generator circuit;
receiving a power supply signal;
comparing the reference voltage to the power supply signal;
in response to a magnitude of the power supply signal being greater than a magnitude of a function of the reference voltage, providing a first output signal having a first logic state;
in response to the magnitude of the power supply signal being less than the magnitude of the function of the reference voltage, providing a second output signal having a second logic state;
in response to the magnitude of the power supply signal being greater than a sum of a magnitude of the reference voltage and a magnitude of a transistor threshold voltage, providing the first output signal having the first logic state; and
in response to the magnitude of the power supply signal being less than the sum of the magnitude of the reference voltage and the magnitude of the transistor threshold voltage, providing the second output signal having the second logic state.
17. The method of claim 16 , further comprising:
in response to the magnitude of the power supply signal being greater than a product of a magnitude of the reference voltage and a voltage divider ratio, providing the first output signal having the first logic state; and
in response to the magnitude of the power supply signal being less than the product of the magnitude of the reference voltage and the voltage divider ratio, providing the second output signal having the second logic state.