Independent gate length tunability for stacked transistors
View Patent ↗A stacked FET structure having independently tuned gate lengths is provided to maximize the benefit of each FET within the stacked FET structure. Notably, a vertically stacked FET structure is provided in which a bottom FET has a different gate length than a top FET. In some embodiments, a dielectric spacer can be present laterally adjacent to the bottom FET and the top FET. In such an embodiment, the dielectric spacer can have a first portion that is located laterally adjacent to the bottom FET that has a different thickness than a second portion of the dielectric spacer that is located laterally adjacent the top FET.
1. A semiconductor structure comprising:
a bottom field effect transistor (FET) and a top FET stacked in a vertical manner one atop the other and separated by an insulator structure, wherein the bottom FET has a first gate length, and the top FET has a second gate length that differs from the first gate length, wherein the bottom FET is a FinFET, and the top FET is a nanosheet FET and wherein the FinFET comprises a semiconductor fin embedded in the insulator structure, and wherein the FinFET comprises a first functional gate structure located beneath the semiconductor fin; and
a dielectric bonding layer located beneath the FinFET and spaced apart from the insulator structure, wherein the dielectric bonding layer is in direct physical contact with a first gate electrode of the first functional gate structure of the FinFET.
2. The semiconductor structure of claim 1 , wherein the first gate length is greater than the second gate length.
3. The semiconductor structure of claim 1 , wherein the first gate length is less than the second gate length.
4. The semiconductor structure of claim 1 , wherein the nanosheet FET comprises a second functional gate structure wrapped around a vertical nanosheet stack of spaced apart semiconductor channel material nanosheets.
5. The semiconductor structure of claim 4 , further comprising a first source/drain region located on the semiconductor fin, and a second source/drain region laterally adjacent to, and in direct physical contact with, the vertical nanosheet stack of spaced apart semiconductor channel material nanosheets.
6. The semiconductor structure of claim 5 , further comprising a first source/drain contact structure contacting the first source/drain region, wherein the first source/drain contact structure is located entirely beneath the semiconductor fin.