Single-phase seven-level inverter
An exemplary system includes an inverter coupled to a DC source, eight power switches and three DC-link capacitors that synthesize seven output voltage levels. In one example the inverter includes a four-level active neutral pointed clamped inverter (4L-ANCP) that includes six power switches of the eight power switches is operated at a switching frequency with a first voltage stress level, and a half-bridge that includes the other two of the eight power switches is coupled to the 4L-ANCP and operated at a fundamental frequency with a second voltage stress, the second voltage stress being higher than the first voltage stress level.
1. A single-phase active neutral point clamped seven-level (SANPC-7L) inverter coupled to a DC source, comprising:
a neutral point clamped inverter;
a half-bridge, wherein the neutral point clamped inverter and the half-bridge includes eight power switches; and three DC-link capacitors that synthesize seven output voltage levels;
wherein the neutral point clamped inverter is a four-level active neutral pointed clamped inverter (4L-ANCP) that includes six power switches of the eight power switches and is operated at a switching frequency with a first voltage stress level;
the half-bridge includes the other two of the eight power switches coupled to the 4L-ANCP and operated at a fundamental frequency with a second voltage stress, the second voltage stress being higher than the first voltage stress level; and
a voltage balance controller is configured to utilize three reference signals and one carrier signal, the one carrier signal is a triangular carrier signal; and
wherein the three reference signals are defined by:
u ref =2 mV m sin(2π f m t );
where m is a modulation index, f m is the fundamental frequency of the inverter, and V m is an amplitude of one of the three reference signals defined by:
u ref1 =|u refx |−V m ;
u ref2 =|u refx /k |; and
u ref3 =|u refx |;
where U refx is a total input of the one of the three reference signals, k is an output of a proportional integration (PI) regulator, and t is a charging time.
2. The inverter of claim 1 , wherein the fundamental frequency is lower than the switching frequency.
3. The inverter of claim 2 , wherein the fundamental frequency is 50 Hz or 60 Hz.
4. The inverter of claim 1 , wherein the voltage-balance controller controls and balances a middle DC-link capacitor voltage at ⅓ of a target DC-link voltage.
5. The inverter of claim 4 , wherein two DC-link capacitor voltages that are not the middle DC-link capacitor voltage are automatically balanced.
6. The inverter of claim 5 , wherein a modulation logic expressions of each of the eight power switches are derived based on a Karnaugh Map technique.
7. A system comprising:
a single DC source;
an inverter coupled to the single DC source, the inverter including seven levels comprising:
a four-level active neutral pointed clamped inverter (4L-ANCP) that includes six power switches operated at a switching frequency with a first voltage stress level;
a half-bridge that includes two power switches is coupled to the 4L-ANCP and operated at a fundamental frequency with a second voltage stress, the second voltage stress being higher than the first voltage stress level; and
three DC-link capacitors that synthesize seven output voltage levels; and
a voltage balance controller is configured to utilize three reference signals and one carrier signal, the carrier signal is a triangular carrier signal; and
wherein the three reference signals are defined by:
u ref =2 mV m sin(2π f m t );
where m is a modulation index, f m is the fundamental frequency of the inverter, and V m is an amplitude of one of the three reference signals defined by:
u ref1 =|u refx |−V m ;
u ref2 =|u refx /k |; and
u ref3 =|u refx |;
where U refx is a total input of the one of the three reference signals, k is an output of a proportional integration (PI) regulator, and t is a charging time.
8. The system of claim 7 , wherein a modulation logic expressions of each of the eight power switches are derived based on a Karnaugh Map technique.
9. A system comprising:
a single DC source;
eight power switches, wherein a modulation logic expression of each of the eight power switches is based on a Karnaugh Map technique;
three DC-link capacitors that synthesize seven output voltage levels;
a four-level active neutral pointed clamped inverter (4L-ANCP) that includes six power switches of the eight power switches is operated at a switching frequency with a first voltage stress level;
a half-bridge that includes the other two of the eight power switches is coupled to the 4L-ANCP and operated at a fundamental frequency with a second voltage stress, the second voltage stress being higher than the first voltage stress level; and
a voltage balance controller is configured to utilize three reference signals and one carrier signal, the carrier signal is a triangular carrier signal;
wherein the three reference signals are defined by:
u ref =2 mV m sin(2π f m t );
where m is a modulation index, f m is the fundamental frequency of the inverter, t is a charging time, and V, is an amplitude of one of the three reference signals defined by:
u ref1 =|u refx |−V m ;
u ref2 =|u refx /k |; and
u ref3 =|u refx |;
where U refx is a total input of the one of the three reference signals, and k is an output of a proportional integration (PI) regulator.
10. The system of claim 9 , wherein:
the modulation logic expression of each of the eight power switches based on the Karnaugh Map technique is:
S
1
=
ABCD
_
❘
"\[LeftBracketingBar]"
❘
"\[RightBracketingBar]"
AB
S
2
=
ABCD
_
❘
"\[LeftBracketingBar]"
❘
"\[RightBracketingBar]"
A
B
_
C
S
3
=
AB
❘
"\[LeftBracketingBar]"
❘
"\[RightBracketingBar]"
AC
❘
"\[LeftBracketingBar]"
❘
"\[RightBracketingBar]"
ABC
_
S
4
=
A
_
B
❘
"\[LeftBracketingBar]"
❘
"\[RightBracketingBar]"
A
_
C
❘
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❘
"\[RightBracketingBar]"
ABC
_
S
5
=
AB
_
C
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❘
"\[RightBracketingBar]"
A
BC
_
D
S
6
=
A
BCD
_
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❘
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A
_
B
S
7
=
A
_
S
8
=
A
where A, B, C, & D are four logical output signals, and S 1 -S 8 are the first through eighth switches, respectively.
11. The system of claim 10 , wherein the three DC-link capacitors are in series and at least one of the DC-link capacitors provides energy to a load while the other DC-link capacitors are charged by the single DC source.
12. The system of claim 10 , wherein the three DC-link capacitors are in series and charged by the single DC source.