Concept for a buffered flipped voltage follower and for a low dropout voltage regulator
Examples relate to a buffered flipped voltage follower circuit arrangement, low dropout voltage regulators, a capacitive digital-to-analog converter, a transceiver for wireless communication, a mobile communication device, a base station transceiver, and to a method for forming a buffered flipped voltage follower circuit arrangement. The buffered flipped voltage follower circuit arrangement comprises a first transistor (M p ) comprising a first terminal, a second terminal and a gate terminal. The buffered flipped voltage follower circuit arrangement comprises a second transistor (M c ) comprising a first terminal, a second terminal and a gate terminal. The buffered flipped voltage follower circuit arrangement comprises a buffer circuit comprising an input terminal and an output terminal. The buffered flipped voltage follower circuit arrangement a feed-forward compensation circuit (−g mf ) comprising an input terminal and an output terminal. The first terminal of the first transistor (M p ) is coupled to a supply voltage of the flipped voltage follower circuit. The second terminal of the first transistor (M p ) is coupled with the first terminal of the second transistor (M c ) and with an output voltage terminal of the buffered flipped voltage follower circuit arrangement. The second terminal of the second transistor (Mc) is coupled with the input terminal of the buffer circuit and with the output terminal of the feed-forward compensation circuit (−g mf ). The gate terminal of the first transistor (MP) is coupled with the output terminal of the buffer circuit and with the input terminal of the feed-forward compensation circuit (−g mf ).
1. A buffered flipped voltage follower circuit arrangement comprising:
A first transistor (M P ) with a first terminal, a second terminal and a gate terminal;
a second transistor (M c ) with a first terminal, a second terminal and a gate terminal;
a buffer circuit with an input terminal and an output terminal; and
a feed-forward compensation circuit (−g m f) with an input terminal and an output terminal,
wherein the first terminal of the first transistor (M P ) is coupled to a supply voltage of the flipped voltage follower circuit,
wherein the second terminal of the first transistor (M P ) is coupled with the first terminal of the second transistor (M c ) and with an output voltage terminal of the buffered flipped voltage follower circuit arrangement,
wherein the second terminal of the second transistor (Mc) is coupled with the input terminal of the buffer circuit and with the output terminal of the feed-forward compensation circuit (−g mf ), and
wherein the gate terminal of the first transistor (M P ) is coupled with the output terminal of the buffer circuit and with the input terminal of the feed-forward compensation circuit (−g m f).
2. The buffered flipped voltage follower circuit arrangement according to claim 1 , wherein the feed-forward compensation circuit (−g m f) is a transconductance circuit.
3. The buffered flipped voltage follower circuit arrangement according to claim 1 , wherein the feed-forward compensation circuit comprises a coupling capacitor (C c ).
4. The buffered flipped voltage follower circuit arrangement according to claim 3 , wherein the feed-forward compensation circuit is coupled with the gate terminal of the first transistor (M P ) via the coupling capacitor (C C ).
5. The buffered flipped voltage follower circuit arrangement according to claim 4 , wherein the feed-forward compensation circuit further comprises a transistor (M F ;kM c ) and a resistor (R B ), wherein a gate terminal of the transistor (M F ) is coupled with a first terminal of the coupling capacitor (C C ) and a first terminal of the resistor (R b ), wherein a second terminal of the resistor (R B ), is coupled to a bias voltage of the buffered flipped voltage follower circuit arrangement, wherein a second terminal of the coupling capacitor (C C ) is the input terminal of the feed-forward compensation circuit, and wherein a first terminal of the transistor (M F ) is the output terminal of the feed-forward compensation circuit.
6. The buffered flipped voltage follower circuit arrangement according to claim 5 , wherein a second terminal of the transistor (M F ) is coupled with a current source I B of the buffered flipped voltage follower circuit arrangement.
7. The buffered flipped voltage follower circuit arrangement according to claim 5 , wherein the bias voltage of the buffered flipped voltage follower circuit arrangement coupled to the second terminal of the resistor is different from a bias voltage of the buffered flipped voltage follower circuit arrangement coupled to a gate terminal of the second transistor (M c ).
8. The buffered flipped voltage follower circuit arrangement according to claim 5 , wherein a second terminal of the transistor (kM c ) is coupled with the second terminal of the first transistor (M P ) and the first terminal of the second transistor (M c ).
9. The buffered flipped voltage follower circuit arrangement according to claim 5 , wherein the transistor (kM c ) of the feed-forward compensation circuit (−g m f) shares a semiconductor structure with the second transistor ((1−k)M c ).
10. The buffered flipped voltage follower circuit arrangement according to claim 3 , wherein the feed-forward compensation circuit is coupled with the second terminal of the second transistor (M c ) via the coupling capacitor (C C ).
11. The buffered flipped voltage follower circuit arrangement according to claim 10 , wherein the feed-forward compensation circuit comprises a third transistor (M F ) and a fifth transistor (M D ), wherein the third and fifth transistors each comprise a first terminal, a second terminal and a gate terminal, where in the first terminal of the third transistor (M F ) is coupled to a supply voltage of the buffered flipped voltage follower circuit arrangement, wherein the gate terminal of the third transistor (M F ) is the input terminal of the feed-forward compensation circuit (−g m f) wherein the second terminal of the third transistor (M F ) is directly or indirectly coupled with the first terminal of the fifth transistor (M D ), wherein the second terminal of the fifth transistor (M D ), is coupled to a ground potential of the buffered flipped voltage follower circuit arrangement.
12. The buffered flipped voltage follower circuit arrangement according to claim 11 , wherein the buffered flipped voltage follower circuit arrangement comprises a fourth transistor (M G ), wherein the second terminal of the third transistor (M F ) is coupled with the first terminal of the fifth transistor (M D ) via the fourth transistor (M G ), wherein the second terminal of the third transistor (M F ) is coupled with a first terminal of the fourth transistor (M G ), wherein a gate terminal of the fourth transistor (M g ) is coupled to a bias voltage of the buffered flipped voltage follower circuit arrangement, wherein a second terminal of the fourth transistor (M G ) is coupled with the first terminal of the fifth transistor (M D ).
13. The buffered flipped voltage follower circuit arrangement according to claim 11 , wherein the coupling capacitor (C c ) comprises a first terminal and a second terminal, wherein the first terminal of the coupling capacitor (C c ) is the output terminal of the feed-forward compensation circuit, and wherein the second terminal of the coupling capacitor (C c ) is coupled with the second terminal of the third transistor (M F ).
14. The buffered flipped voltage follower circuit arrangement according to claim 11 , wherein the coupling capacitor (C c ) comprises a first terminal and a second terminal, wherein the first terminal of the coupling capacitor (C c ) is the output terminal of the feed-forward compensation circuit, and wherein the second terminal of the coupling capacitor (C c ) is coupled with the first terminal of the fifth transistor (M D ).
15. The buffered flipped voltage follower circuit arrangement according to claim 11 , wherein the third transistor (M F ) shares a semiconductor structure with the first transistor (M P ).
16. The buffered flipped voltage follower circuit arrangement according to claim 1 , wherein the buffer circuit comprises a source follower circuit.
17. The buffered flipped voltage follower circuit arrangement according to claim 1 , wherein the buffer circuit comprises a super source follower circuit.
18. The buffered flipped voltage follower circuit arrangement according to claim 1 , wherein the gate terminal of the second transistor (M c ) is coupled to a bias voltage (V B ) of the buffered flipped voltage follower circuit arrangement.
19. The buffered flipped voltage follower circuit arrangement according to claim 1 , wherein the second terminal of the second transistor (M c ) is coupled to a biasing current source of the buffered flipped voltage follower circuit arrangement.
20. A low drop out voltage regulator comprising the buffered flipped voltage follower circuit arrangement according to claim 1 .
21. A capacitive digital-to-analog converter comprising a low dropout voltage regulator according to claim 20 .
22. Method for forming a buffered flipped voltage follower circuit arrangement, the method comprising:
forming a first transistor (M P ) comprising a first terminal, a second terminal and a gate terminal;
forming a second transistor (M c ) comprising a first terminal, a second terminal and a gate terminal;
forming a buffer circuit comprising an input terminal and an output terminal;
forming a feed-forward compensation circuit (−g m f) comprising an input terminal and an output terminal; and
forming interconnections between the first transistor (M P ), the second transistor (M C ), the buffer circuit and the feed-forward compensation circuit (−g m f),
wherein the first terminal of the first transistor (M P ) is coupled to a supply voltage of the flipped voltage follower circuit,
wherein the second terminal of the first transistor (M P ) is coupled with the first terminal of the second transistor (M C ) and with an output voltage terminal of the buffered flipped voltage follower circuit arrangement,
wherein the second terminal of the second transistor (M c ) is coupled with the input terminal of the buffer circuit and with the output terminal of the feed-forward compensation circuit (−g mf ), and
wherein the gate terminal of the first transistor (M P ) is coupled with the output terminal of the buffer circuit and with the input terminal of the feed-forward compensation circuit (−g m f).