Maintaining phase coherence for a fractional-N PLL
A fractional-N phase-locked loop (PLL) that maintains phase coherence for an output signal with a plurality of possible output frequencies. The fractional-N PLL includes an oscillator, a phase detector to receive a reference clock signal and a feedback signal, and a multi-modulus divider coupled in a feedback path between the oscillator and the phase detector. A multi-modulus pattern generator supplies a drive pattern to the multi-modulus divider to achieve a desired change in frequency of the output signal. The multi-modulus pattern generator initiates the drive pattern at a boundary time to cause the output signal to have a substantially repeatable phase when restarting switching from any one of the output frequencies to any other of the output frequencies.
1. An apparatus comprising:
a fractional-N phase-locked loop (PLL) to generate an output signal having one of a plurality of output frequencies, the fractional-N PLL including,
an oscillator;
a phase detector to receive a reference clock signal and a feedback signal; and
a multi-modulus divider coupled in a feedback path between the oscillator and the phase detector; and
a multi-modulus pattern generator to supply a drive pattern to the multi-modulus divider to achieve a desired change in frequency of the output signal, the multi-modulus pattern generator initiating the drive pattern at a boundary time to cause the output signal to have a repeatable phase when switching from any one of the output frequencies to any other of the output frequencies.
2. The apparatus as recited in claim 1 wherein the boundary time is separated from a previous boundary time by a boundary time interval and the boundary time interval is a predetermined number of cycles of the reference clock signal.
3. The apparatus as recited in claim 2 wherein the boundary time interval is the same for all of the plurality of output frequencies.
4. The apparatus as recited in claim 1 further comprising a crystal oscillator to supply the reference clock signal.
5. The apparatus as recited in claim 1 wherein the plurality of output frequencies are spaced equally apart.
6. The apparatus as recited in claim 1 further wherein the drive pattern is a digital pattern having a ones density to achieve a desired one of the plurality of output frequencies and an average residue having an integer value greater than or equal to zero.
7. The apparatus as recited in claim 6 wherein the drive pattern supplied to the multi-modulus divider has an original portion with a ones density corresponding to the desired one of the output frequencies and a mirror image of the original portion and the original portion and the mirror image are interleaved.
8. The apparatus as recited in claim 6 further comprising a sigma delta modulator to supply respective drive patterns for the plurality of output frequencies and the sigma delta modulator has a signal transfer function (STF) equal to one.
9. The apparatus as recited in claim 1 wherein the drive pattern supplied to the multi-modulus divider is an even function.
10. The apparatus as recited in claim 1 wherein another drive pattern for a frequency change is initiated offset from another instance of the boundary time responsive to a phase compensation request.
11. The apparatus as recited in claim 1 further comprising a plurality of sources to supply a respective plurality of drive patterns for the multi-modulus divider.
12. The apparatus as recited in claim 11 further comprising:
a selector circuit to select one of the drive patterns as the drive pattern; and
wherein the plurality of sources include,
a first delta sigma modulator to supply a first drive pattern based on a first desired frequency; and
a second delta sigma modulator to supply a second drive pattern based on a second desired frequency.
13. The apparatus as recited in claim 1 wherein the multi-modulus divider is a multi-bit multi-modulus divider.
14. A method for generating an output signal comprising:
supplying a drive pattern to a multi-modulus divider of a fractional-N phase locked loop to achieve a desired change in frequency of the output signal from a first frequency of a plurality of output frequencies to a second frequency of the plurality of output frequencies; and
initiating supplying the drive pattern at a boundary time to thereby cause the output signal to have a repeatable phase when switching the output signal from any one of a plurality of output frequencies to any other of the plurality of output frequencies.
15. The method as recited in claim 14 further comprising:
supplying the drive pattern from a sigma delta modulator; and
resetting state variables of the sigma delta modulator to a known state prior to supplying the drive pattern at the boundary time.
16. The method as recited in claim 14 further comprising:
supplying a reference clock signal to the fractional-N phase-locked loop; and
determining the boundary time by counting a boundary time interval from a previous boundary time, the boundary time interval being a predetermined number of cycles of the reference clock signal and the boundary time interval being determined according to a frequency of the reference clock signal and the output frequencies.
17. The method as recited in claim 16 further comprising supplying the reference clock signal from a crystal oscillator.
18. The method as recited in claim 14 further comprising supplying the drive pattern as a digital pattern having a ones density to achieve a desired one of the plurality of output frequencies and having an average residue that is an integer value greater than or equal to zero.
19. The method as recited in claim 18 generating the drive pattern supplied to the multi-modulus divider using an original portion with a ones density corresponding to the desired one of the output frequencies that is interleaved with a mirror image portion of the original portion.
20. The method as recited in claim 14 further comprising generating the drive pattern supplied to the multi-modulus divider as an even function.
21. The method as recited in claim 14 further comprising supplying the drive pattern from a sigma delta modulator having a signal transfer function (STF) equal to one.
22. The method as recited in claim 14 further comprising:
supplying the drive pattern from a first delta sigma modulator for the first frequency; and
responsive to a request to change to a second frequency of the plurality of output frequencies, activating a second delta sigma modulator to supply a second drive pattern corresponding to the second frequency.
23. The method as recited in claim 14 further comprising initiating another drive pattern for a frequency change from the second frequency to another of the plurality of output frequencies at an offset from the boundary time responsive to a phase compensation request.
24. An apparatus comprising:
a fractional-N phase-locked loop (PLL) to generate an output signal having one of a plurality of output frequencies and the PLL is coupled to receive a reference clock signal; and
a pattern generator to supply respective drive patterns to a multi-modulus divider of the PLL, the respective drive patterns corresponding to the plurality of output frequencies;
wherein the pattern generator initiates supplying the respective drive patterns at respective boundary times, each of the respective boundary times separated from a previous boundary time by a boundary time interval corresponding to a predetermined number of reference clock cycles; and
wherein the output frequencies have a known and repeatable phase.