Memory device, the operation method thereof and memory system

1. A memory device, comprising a memory cell array and a peripheral circuit coupled to the memory cell array;

the memory cell array comprises a plurality of memory planes;

the peripheral circuit comprises a plurality of selected voltage selection circuits corresponding to the plurality of memory planes, a plurality of global word line voltage selection circuits respectively corresponding to each memory plane, and a plurality of local word line voltage selection circuits respectively corresponding to each memory plane;

the plurality of selected voltage selection circuits are configured to select a voltage from a plurality of selected voltages to output to the global word line voltage selection circuits; the global word line voltage selection circuits are configured to select a voltage from unselected voltages and the voltage output from the plurality of selected voltage selection circuits to output to the local word line voltage selection circuits;

during a program operation, the plurality of memory planes share the plurality of selected voltage selection circuits; and

during a read operation, each memory plane uses a part of the plurality of selected voltage selection circuits respectively to perform voltage selection.

2. The memory device according to claim 1 , wherein

during the program operation, a number of the selected voltages corresponding to the plurality of memory planes is a, and a number of the selected voltage selection circuits corresponding to the plurality of memory planes is at least a;

during the read operation, a number of the selected voltages corresponding to each memory plane is b, and a number of the selected voltage selection circuits corresponding to each memory plane is at least b; and

a number of the memory planes is c, and a relationship among a, b, and c is: a≥b*c; wherein both a and b are positive integers greater than 0, and c is a positive integer greater than 1.

3. The memory device according to claim 2 , wherein

the peripheral circuit further comprises a plurality of global word lines corresponding to the global word line voltage selection circuits one-to-one;

during the program operation, the number of the selected voltage selection circuits corresponding to the plurality of memory planes is a, and adjacent a global word lines on each memory plane correspond to different selected voltage selection circuits; and

during the read operation, the global word lines on different memory planes correspond to different selected voltage selection circuits, the number of the selected voltage selection circuits corresponding to each memory plane is b, and adjacent b global word lines on each memory plane correspond to different selected voltage selection circuits.

4. The memory device according to claim 1 , wherein

the peripheral circuit further comprises a plurality of unselected voltage selection circuits corresponding to the plurality of memory planes; each unselected voltage selection circuit corresponds to the plurality of local word line voltage selection circuits on one memory plane, each local word line voltage selection circuit corresponds to one unselected voltage selection circuit;

each of the plurality of unselected voltage selection circuits is configured to select a voltage from at least one unselected voltage to output to the local word line voltage selection circuits;

during the program operation, the plurality of memory planes share the plurality of unselected voltage selection circuits; and

during the read operation, each memory plane uses a part of the plurality of unselected voltage selection circuits respectively to perform voltage selection.

5. The memory device according to claim 4 , wherein

during the program operation, a number of the unselected voltages corresponding to the plurality of memory planes is d, and a number of the unselected voltage selection circuits corresponding to the plurality of memory planes is at least d;

during the read operation, a number of the unselected voltages corresponding to each memory plane is e, and a number of the unselected voltage selection circuits corresponding to each memory plane is at least e; and

a number of the memory planes is c, and a relationship among c, d, and e is: d≥e*c;

wherein both d and e are positive integers greater than 0, and c is a positive integer greater than 1.

6. The memory device according to claim 4 , wherein

each of the memory planes comprises a plurality of word lines;

the peripheral circuit further comprises a plurality of global word lines corresponding to the global word line voltage selection circuits one-to-one, and a plurality of local word lines corresponding to the local word line voltage selection circuits one-to-one, wherein each of the global word lines corresponds to the plurality of local word lines; each local word line corresponds to one global word line, and each local word line corresponds to one word line;

the global word line voltage selection circuits output the voltage to the local word line voltage selection circuits through the global word lines; and

the local word line voltage selection circuits output the voltage to corresponding word lines through the local word lines.

7. The memory device according to claim 4 , wherein the selected voltage selection circuits, the global word line voltage selection circuits, the local word line voltage selection circuits, and the unselected voltage selection circuits all comprise a multiplexer.

8. A memory system, comprising one or more memory devices and a memory controller coupled to and configured to control the one or more memory devices, wherein each of the memory devices comprises a memory cell array and a peripheral circuit coupled to the memory cell array;

the memory cell array comprises a plurality of memory planes;

the peripheral circuit comprises a plurality of selected voltage selection circuits corresponding to the plurality of memory planes, a plurality of global word line voltage selection circuits respectively corresponding to each memory plane, and a plurality of local word line voltage selection circuits respectively corresponding to each memory plane;

the plurality of selected voltage selection circuits are configured to select a voltage from a plurality of selected voltages to output to the global word line voltage selection circuits; the global word line voltage selection circuits are configured to select a voltage from unselected voltages and the voltage output from the plurality of selected voltage selection circuits to output to the local word line voltage selection circuits;

during a program operation, the plurality of memory planes share the plurality of selected voltage selection circuits; and

during a read operation, each memory plane uses a part of the plurality of selected voltage selection circuits respectively to perform voltage selection.

9. The memory system according to claim 8 , wherein

during the program operation, a number of the selected voltages corresponding to the plurality of memory planes is a, and a number of the selected voltage selection circuits corresponding to the plurality of memory planes is at least a;

during the read operation, a number of the selected voltages corresponding to each memory plane is b, and a number of the selected voltage selection circuits corresponding to each memory plane is at least b; and

a number of the memory planes is c, and a relationship among a, b, and c is: a≥b*c;

wherein both a and b are positive integers greater than 0, and c is a positive integer greater than 1.

10. The memory system according to claim 9 , wherein

the peripheral circuit further comprises a plurality of global word lines corresponding to the global word line voltage selection circuits one-to-one;

during the program operation, the number of the selected voltage selection circuits corresponding to the plurality of memory planes is a, and adjacent a global word lines on each memory plane correspond to different selected voltage selection circuits; and

during the read operation, the global word lines on different memory planes correspond to different selected voltage selection circuits, the number of the selected voltage selection circuits corresponding to each memory plane is b, and adjacent b global word lines on each memory plane correspond to different selected voltage selection circuits.

11. The memory system according to claim 8 , wherein

the peripheral circuit further comprises a plurality of unselected voltage selection circuits corresponding to the plurality of memory planes; each unselected voltage selection circuit corresponds to the plurality of local word line voltage selection circuits on one memory plane, each local word line voltage selection circuit corresponds to one unselected voltage selection circuit;

each of the plurality of unselected voltage selection circuits is configured to select a voltage from at least one unselected voltage to output to the local word line voltage selection circuits;

during the program operation, the plurality of memory planes share the plurality of unselected voltage selection circuits; and

during the read operation, each memory plane uses a part of the plurality of unselected voltage selection circuits respectively to perform voltage selection.

12. The memory system according to claim 11 , wherein

During the program operation, a number of the unselected voltages corresponding to the plurality of memory planes is 61 , and a number of the unselected voltage selection circuits corresponding to the plurality of memory planes is at least ci;

during the read operation, a number of the unselected voltages corresponding to each memory plane is e, and a number of the unselected voltage selection circuits corresponding to each memory plane is at least e; and

a number of the memory planes is c, and a relationship among c, d, and e is: d≥e*c: wherein both d and e are positive integers greater than 0, and c is a positive integer greater than 1.

13. The memory system according to claim 11 , wherein

each of the memory planes comprises a plurality of word lines;

the peripheral circuit further comprises a plurality of global word lines corresponding to the global word line voltage selection circuits one-to-one, and a plurality of local word lines corresponding to the local word line voltage selection circuits one-to-one, wherein each of the global word lines corresponds to the plurality of local word lines; each local word line corresponds to one global word line, and each local word line corresponds to one word line;

the global word line voltage selection circuits output the voltage to the local word line voltage selection circuits through the global word lines; and

the local word line voltage selection circuits output the voltage to corresponding word lines through the local word lines.

14. The memory system according to claim 11 , wherein the selected voltage selection circuits, the global word line voltage selection circuits, the local word line voltage selection circuits, and the unselected voltage selection circuits all comprise a multiplexer.

15. The memory system according to claim 8 , wherein the memory system comprises a memory card or a solid state hard disk.

16. A method for operating a memory device, wherein the memory device comprises a memory cell array and a peripheral circuit coupled to the memory cell array;

the memory cell array comprises a plurality of memory planes;

the peripheral circuit comprises a plurality of selected voltage selection circuits corresponding to the plurality of memory planes, a plurality of global word line voltage selection circuits respectively corresponding to each memory plane; and a plurality of local word line voltage selection circuits respectively corresponding to each memory plane;

the plurality of selected voltage selection circuits are configured to select a voltage from a plurality of selected voltages to output to the global word line voltage selection circuits; the global word line voltage selection circuits are configured to select a voltage from unselected voltages and the voltage output from the plurality of selected voltage selection circuits to output to the local word line voltage selection circuits;

the method comprises:

receiving a first instruction, wherein the first instruction is configured to simultaneously perform a program operation on the plurality of memory planes;

applying a plurality of different voltages output by the plurality of selected voltage selection circuits to each memory plane in response to the first instruction;

receiving a second instruction, wherein the second instruction is configured to perform a read operation on the plurality of memory planes; and

applying a part of the plurality of different voltages output by the plurality of selected voltage selection circuits respectively to different memory planes in response to the second instruction.

17. The method according to claim 16 , wherein

during the program operation performed on the plurality of memory planes simultaneously, a number of the selected voltages corresponding to the plurality of memory planes is a, and a number of the selected voltage selection circuits corresponding to the plurality of memory planes is at least a;

during the read operation performed on the plurality of memory planes, a number of the selected voltages corresponding to each memory plane is b, and a number of the selected voltage selection circuits corresponding to each memory plane is at least b; and

a number of the memory planes is c, and a relationship among a, b, and c is: a≥b*c; wherein both a and b are positive integers greater than 0, and c is a positive integer greater than 1.

18. The method according to claim 17 , wherein

the peripheral circuit further comprises a plurality of global word lines corresponding to the global word line voltage selection circuits one-to-one;

during the program operation performed on the plurality of memory planes simultaneously, the number of the selected voltage selection circuits corresponding to the plurality of memory planes is a, and adjacent a global word lines on each memory plane correspond to different selected voltage selection circuits; and

during the read operation performed on the plurality of memory planes, the global word lines on different memory planes correspond to different selected voltage selection circuits, the number of the selected voltage selection circuits corresponding to each memory plane is b, and adjacent b global word lines on each memory plane correspond to different selected voltage selection circuits.

19. The method according to claim 16 , wherein

the peripheral circuit further comprises a plurality of unselected voltage selection circuits corresponding to the plurality of memory planes; each unselected voltage selection circuit corresponds to the plurality of local word line voltage selection circuits on one memory plane, each local word line voltage selection circuit corresponds to one unselected voltage selection circuit;

each of the plurality of unselected voltage selection circuits is configured to select a voltage from at least one unselected voltage to output to the local word line voltage selection circuits;

the method further comprises:

applying a plurality of different voltages output by the plurality of unselected voltage selection circuits to each memory plane in response to the first instruction; and

applying a part of the plurality of different voltages output by the plurality of unselected voltage selection circuits respectively to different memory planes in response to the second instruction.

20. The method according to claim 19 , wherein

during the program operation, a number of the unselected voltages corresponding to the plurality of memory planes is d, and a number of the unselected voltage selection circuits corresponding to the plurality of memory planes is at least d;

during the read operation, a number of the unselected voltages corresponding to each memory plane is e, and a number of the unselected voltage selection circuits corresponding to each memory plane is at least e; and

a number of the memory planes is c, and a relationship among c, d and, e is: d≥e*c; wherein both d and e are positive integers greater than 0, and c is a positive integer greater than 1.