Array substrate including connection layer and display panel having the same
View Patent ↗An array substrate and a display panel are provided. The array substrate includes a substrate, a planarization layer, a connection layer, and an anode layer. The planarization layer is disposed on a side of the substrate and is provided with a first via hole. The connection layer includes a connecting portion. The connecting portion is disposed in the first via hole and extends to a surface of the planarization layer. The anode layer is disposed on a surface of the connecting portion away from the planarization layer. In the array substrate, the connecting portion is disposed between the planarization layer and the anode layer, which can prevent pixels of the display panel from generating black dots.
1. An array substrate, comprising:
a substrate;
a planarization layer disposed on a side of the substrate and provided with a first via hole;
a connection layer comprising a connecting portion, wherein the connecting portion is disposed in the first via hole and extends to a surface of the planarization layer; and
an anode layer disposed on a surface of the connecting portion away from the planarization layer,
wherein the connecting portion comprises:
a first sub-connecting portion covering the first via hole; and
a second sub-connecting portion disposed on the surface of the planarization layer, wherein there is a gap between the first sub-connecting portion and the second sub-connecting portion, the anode layer covers the first sub-connecting portion, the second sub-connecting portion, and a part of the planarization layer located at the gap, and the first sub-connecting portion and the second sub-connecting portion are connected by the anode layer.
2. The array substrate according to claim 1 , further comprising a first metal layer, a buffer layer, a semiconductor layer, a gate insulating layer, a gate layer, an interlayer dielectric layer, a second metal layer, and a passivation layer disposed in sequence.
3. The array substrate according to claim 2 , wherein the second metal layer comprises a source electrode, a drain electrode, and a first binding portion, the source electrode is connected to the connecting portion, and the first binding portion is connected to the first metal layer.
4. The array substrate according to claim 3 , wherein the planarization layer is further provided with a second via hole, the connection layer further comprises a second binding portion, and the second binding portion is disposed in the second via hole and is connected to the first binding portion.
5. The array substrate according to claim 4 , further comprising a pixel defining layer, wherein the pixel defining layer is provided with a first opening and a second opening, the first opening exposes the anode layer, and the second opening corresponds to the second via hole and exposes the second binding portion.
6. The array substrate according to claim 2 , wherein the second metal layer further comprises a first electrode plate connected to the first metal layer.
7. The array substrate according to claim 1 , wherein the connection layer is made of one or more of molybdenum, titanium, molybdenum/titanium, a titanium alloy, and indium tin oxide.
8. The array substrate according to claim 1 , wherein the anode layer comprises:
a first sublayer made of indium tin oxide or indium zinc oxide;
a second sublayer made of silver or silver alloy; and
a third sublayer made of indium tin oxide or indium zinc oxide.
9. The array substrate according to claim 1 , wherein a part of the connecting portion between the anode layer and the planarization layer has a thickness of 30 nm to 300 nm.
10. A display panel, comprising an array substrate, wherein the array substrate comprises:
a substrate;
a planarization layer disposed on a side of the substrate and provided with a first via hole;
a connection layer comprising a connecting portion, wherein the connecting portion is disposed in the first via hole and extends to a surface of the planarization layer; and
an anode layer disposed on a surface of the connecting portion away from the planarization layer,
wherein the connecting portion comprises:
a first sub-connecting portion covering the first via hole; and
a second sub-connecting portion disposed on the surface of the planarization layer, wherein there is a gap between the first sub-connecting portion and the second sub-connecting portion, the anode layer covers the first sub-connecting portion, the second sub-connecting portion, and a part of the planarization layer located at the gap, and the first sub-connecting portion and the second sub-connecting portion are connected by the anode layer.
11. The display panel according to claim 10 , wherein the array substrate further comprises a first metal layer, a buffer layer, a semiconductor layer, a gate insulating layer, a gate layer, an interlayer dielectric layer, a second metal layer, and a passivation layer disposed in sequence.
12. The display panel according to claim 11 , wherein the second metal layer comprises a source electrode, a drain electrode, and a first binding portion, the source electrode is connected to the connecting portion, and the first binding portion is connected to the first metal layer.
13. The display panel according to claim 12 , wherein the planarization layer is further provided with a second via hole, the connection layer further comprises a second binding portion, and the second binding portion is disposed in the second via hole and is connected to the first binding portion.
14. The display panel according to claim 13 , wherein the array substrate further comprises a pixel defining layer, the pixel defining layer is provided with a first opening and a second opening, the first opening exposes the anode layer, and the second opening corresponds to the second via hole and exposes the second binding portion.
15. The display panel according to claim 11 , wherein the second metal layer further comprises a first electrode plate connected to the first metal layer.
16. The display panel according to claim 10 , wherein the connection layer is made of one or more of molybdenum, titanium, molybdenum/titanium, a titanium alloy, and indium tin oxide.
17. The display panel according to claim 10 , wherein the anode layer comprises:
a first sublayer made of indium tin oxide or indium zinc oxide;
a second sublayer made of silver or silver alloy; and
a third sublayer made of indium tin oxide or indium zinc oxide.
18. The display panel according to claim 10 , wherein a part of the connecting portion between the anode layer and the planarization layer has a thickness of 30 nm to 300 nm.
19. An array substrate, comprising:
a substrate;
a planarization layer disposed on a side of the substrate and provided with a first via hole;
a connection layer comprising a connecting portion, wherein the connecting portion is disposed in the first via hole and extends to a surface of the planarization layer; and
an anode layer disposed on a surface of the connecting portion away from the planarization layer,
wherein the array substrate further comprises a first metal layer, a buffer layer, a semiconductor layer, a gate insulating layer, a gate layer, an interlayer dielectric layer, a second metal layer, and a passivation layer disposed in sequence,
wherein the second metal layer comprises a source electrode, a drain electrode, and a first binding portion, the source electrode is connected to the connecting portion, and the first binding portion is connected to the first metal layer.