IP Library › Granted Patent US 12,118,217
Granted Patent B2
US 12,118,217 · App. 18/059,356 · Granted Oct 15, 2024

Memory system, memory controller and method for operating memory system, capable of determining target meta memory block on the basis of detected target state

Inventor: Jang Hun Yun (Icheon, KR)
Assignee: SK hynix Inc.
G06F3/0619G06F3/064G06F3/0653G06F3/0659G06F3/0679
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Quick Facts
Patent No.
US 12,118,217
App. No.
18/059,356
Granted
Oct 15, 2024
Kind
B2
Abstract

In a memory system, one or more target meta memory blocks to which an entirety or a part of meta data is to be written are determined on the basis of a detected target state from among a plurality of target states. The one or more target meta memory block may be selected from among a plurality of meta memory blocks on the basis of a number of detected target states among the plurality of target states.

Claims (52)

1. A memory system comprising:

a memory device including a plurality of meta memory blocks to which meta data is permitted to be written; and

a memory controller configured to determine, based on a number of detected target states among a plurality of target states indicating operation of the memory device may be unstable, at least one of the plurality of meta memory blocks as a target meta memory block to which an entirety or a part of types of the meta data is to be written,

wherein when the number of detected target states among the plurality of target states is equal to or greater than a first value, the memory controller determines:

a first meta memory block among the plurality of meta memory blocks as a first target meta memory block in which the metadata of a master data type and a history data type are to be stored, and

a second meta memory block among the plurality of meta memory blocks as a second target meta memory block in which the metadata of a map data type is to be stored.

2. The memory system of claim 1 , wherein the plurality of target states include:

a first state corresponding to a first number of times, which is a number of times that respective numbers of error bits occurring in operations of reading data from the memory device during a first time period were equal to or greater than a first threshold error bit number, being equal to or greater than a first threshold number of times,

a second state corresponding to a temperature of the memory device not being within a preset temperature range,

a third state corresponding to a number of times a sudden power-off has occurred during a second time period being equal to or greater than a second threshold number of times, and

a fourth state corresponding to an occurrence of a program status fail, an uncorrectable error correction code, an erase status fail, or a combination thereof.

3. The memory system of claim 1 , wherein the types of the meta data includes:

the master data type including data used during a booting operation of the memory system,

the history data type including system data capable of being changed during a runtime, and

the map data type indicating mapping information between logical addresses and physical addresses.

4. The memory system according to claim 3 , wherein the map data type includes first level map data and second level map data.

5. The memory system according to claim 1 , wherein when the number of detected target states is equal to or greater than the first value, the memory controller sets one or more meta memory blocks other than the first meta memory block and second meta memory block among the plurality of meta memory blocks to a closed state.

6. The memory system according to claim 1 ,

wherein when the number of detected target states is equal to or greater than a second value, the memory controller determines a third meta memory block as the target meta memory block in which all meta data are to be stored, and

wherein the second value is greater than the first value.

7. The memory system according to claim 6 , wherein when the number of detected target states is equal to or greater than the second value, the memory controller sets a meta memory block not determined as the target meta memory block in which meta data are to be stored to a closed state.

8. A method for operating a memory system, comprising:

determining a detected target state among a plurality of target states, indicating operation of the memory device may be unstable, set in advance; and

determining at least one target meta memory block to which entirety or a part of types of meta data is to be written, among a plurality of meta memory blocks to which the meta data is permitted to be written, based on a number of detected target state,

wherein determining the at least one target meta memory block comprises:

when the number of detected target states among the plurality of target states is equal to or greater than a first value, determining:

a first meta memory block among the plurality of meta memory blocks as a target meta memory block in which the metadata of a master data type and a history data type are to be stored, and

a second meta memory block among the plurality of meta memory blocks as a target meta memory block in which the metadata of a map data type is to be stored.

9. The method according to claim 8 , wherein the plurality of target states include:

a first state corresponding to a first number of times, which is a number of times that respective numbers of error bits occurring in operations of reading data from the memory device during a first time period were equal to or greater than a first threshold error bit number, being equal to or greater than a first threshold number of times,

a second state corresponding to a temperature of the memory device not being within a preset temperature range,

a third state corresponding to a number of times a sudden power-off has occurred during a second time period being equal to or greater than a second threshold number of times, and

a fourth state corresponding to an occurrence of a program status fail, an uncorrectable error correction code, an erase status fail, or a combination thereof.

10. The method according to claim 8 , wherein the types of the meta data includes:

the master data type including data used during a booting operation of the memory system,

the history data type including system data capable of being changed during a runtime, and

the map data type indicating mapping information between logical addresses and physical addresses.

11. The method according to claim 10 , wherein the map data type includes first level map data and second level map data.

12. The method according to claim 8 , wherein determining that at least one target meta memory block further comprises:

when the number of detected target states is equal to or greater than the first value, setting one or more meta memory blocks other than the first meta memory block and second meta memory block among the plurality of meta memory blocks to a closed state.

13. The method according to claim 8 , wherein determining the at least one target meta memory block comprises:

when the number of detected target states is equal to or greater than a second value, determining a third meta memory block as the target meta memory block in which all meta data are to be stored,

wherein the second value is greater than the first value.

14. The method according to claim 13 , wherein determining the at least one target meta memory block further comprises:

when the number of detected target states among the plurality of target states is equal to or greater than the second value, setting a meta memory block not determined as the target meta memory block in which meta data are to be stored to a closed state.

15. A memory controller comprising:

a memory interface capable of communicating with a memory device including a plurality of meta memory blocks to which meta data is permitted to be written; and

a control circuit configured to determine, based on a number of detected target states among a plurality of target states which indicate operation of the memory device may be unstable, at least one of the plurality of meta memory blocks as a target meta memory block to which an entirety or a part of types of the meta data is to be written,

wherein determining the at least one target meta memory block comprises:

when the number of detected target states among the plurality of target states is equal to or greater than a first value, determining:

a first meta memory block among the plurality of meta memory blocks as a target meta memory block in which the metadata of a master data type and a history data type are to be stored, and

a second meta memory block among the plurality of meta memory blocks as a target meta memory block in which the metadata of a map data type is to be stored.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 29, 2022
From: YUN, JANG HUN
To: SK HYNIX INC.
Reel/Frame 061905/0792 →
Priority Claims (1)
KR 10-2022-0093562 · Jul 28, 2022 · national
Continuity (1)
Related Publication 20240036741A1 · Feb 1, 2024