IP Library › Granted Patent US 12,118,220
Granted Patent B2
US 12,118,220 · App. 18/200,685 · Granted Oct 15, 2024

Elastic persistent memory regions

Inventors: Joseph H. Steinmetz (Loomis, CA); Luca Bert (San Jose, CA); William Akin (Morgan Hill, CA)
Assignee: Micron Technology, Inc.
G06F3/0631G06F3/0604G06F3/0644G06F3/068G06F12/0808G06F2212/1044
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Quick Facts
Patent No.
US 12,118,220
App. No.
18/200,685
Granted
Oct 15, 2024
Kind
B2
Abstract

A system includes a memory and at least one processing device, operatively coupled to the memory, to perform operations including causing a region of a non-volatile memory device to be accessible through a persistent memory region (PMR) of a volatile memory device. The PMR utilizes a power protection mechanism to prevent data loss in an event of power loss.

Claims (32)

1. A system comprising:

a memory; and

at least one processing device, operatively coupled to the memory, to perform operations comprising:

causing a region of a non-volatile memory device to be accessible through a persistent memory region (PMR) of a volatile memory device, wherein the PMR utilizes a power protection mechanism to prevent data loss in an event of power loss; and

managing PMR caching with respect to the PMR by using a caching mechanism that manages page eviction based on a set of key registers.

2. The system of claim 1 , wherein the operations further comprise writing data from the volatile memory device to the non-volatile memory device in the event of power loss.

3. The system of claim 1 , wherein the volatile memory device includes a Double Data Rate (DDR) device.

4. The system of claim 1 , a wherein the set of key registers is internal to a controller.

5. The system of claim 1 , wherein the set of key registers comprises at least one: a key register indicating a size of the PMR, a key register indicating a size of each page of the PMR, a key register indicating a number of pages of the PMR, or a key register controlling restoration and eviction of PMR data.

6. The system of claim 1 , wherein the operations further comprise:

receiving a PMR access request to perform a data operation; and

performing the data operation using the caching mechanism.

7. The system of claim 1 , wherein the operations further comprise managing at least one of shutdown or startup using the caching mechanism.

8. A method comprising:

causing, by a processing device, a region of a non-volatile memory device to be accessible through a persistent memory region (PMR) of a volatile memory device, wherein the PMR utilizes a power protection mechanism to prevent data loss in an event of power loss; and

managing, by the processing device, PMR caching with respect to the PMR by using a caching mechanism that manages page eviction based on a set of key registers.

9. The method of claim 8 , further comprising writing, by the processing device, data from the volatile memory device to the non-volatile memory device in the event of power loss.

10. The method of claim 8 , wherein the volatile memory device includes a Double Data Rate (DDR) device.

11. The method of claim 8 , wherein the set of key registers comprises at least one: a key register indicating a size of the PMR, a key register indicating a size of each page of the PMR, a key register indicating a number of pages of the PMR, or a key register controlling restoration and eviction of PMR data.

12. The method of claim 8 , further comprising:

receiving, by the processing device, a PMR access request to perform a data operation; and

performing, by the processing device, the data operation using the caching mechanism.

13. The method of claim 8 , further comprising managing, by the processing device using the caching mechanism, at least one of shutdown or startup.

14. A non-transitory computer-readable storage medium comprising instructions that, when executed by a processing device, cause the processing device to perform operations comprising:

causing a region of a non-volatile memory device to be accessible through a persistent memory region (PMR) of a volatile memory device, wherein the PMR utilizes a power protection mechanism to prevent data loss in an event of power loss; and

managing, by the processing device, PMR caching with respect to the PMR by using a caching mechanism that manages page eviction based on a set of key registers.

15. The non-transitory computer-readable storage medium of claim 14 , wherein the operations further comprise writing data from the volatile memory device to the non-volatile memory device in the event of power loss.

16. The non-transitory computer-readable storage medium of claim 14 , wherein the set of key registers comprises at least one: a key register indicating a size of the PMR, a key register indicating a size of each page of the PMR, a key register indicating a number of pages of the PMR, or a key register controlling restoration and eviction of PMR data.

17. The non-transitory computer-readable storage medium of claim 14 , wherein the operations further comprise:

receiving a PMR access request to perform a data operation; and

performing the data operation using the caching mechanism.

18. The non-transitory computer-readable storage medium of claim 14 , wherein the operations further comprise managing at least one of shutdown or startup using the caching mechanism.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 23, 2023
From: STEINMETZ, JOSEPH H.; BERT, LUCA; AKIN, WILLIAM
To: MICRON TECHNOLOGY, INC.
Reel/Frame 063729/0603 →
Continuity (2)
Continuation 17232971 · Apr 16, 2021
Related Publication 20230297256A1 · Sep 21, 2023