IP Library Granted Patent US 12,119,256
Granted Patent B2
US 12,119,256 · App. 17/467,250 · Granted Oct 15, 2024

Replacing end effectors in semiconductor processing systems

Inventor: Dongyang Chen (Chandler, AZ)
Assignee: ASM IP Holding B.V.
H01L21/68707
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Quick Facts
Patent No.
US 12,119,256
App. No.
17/467,250
Granted
Oct 15, 2024
Kind
B2
Abstract

A method of replacing an end effector for wafer handling in a semiconductor processing system includes fixing a first end effector jig to a first stage and a second end effector jig to a second stage of the load lock module; positioning a first end effector at the first end effector jig and a second end effector at the second end effector jig, the second end effector fixed relative to the first end effector; and fixing the second end effector to the second end effector jig. The first end effector is replaced with a replacement end effector and the semiconductor processing system returned to production without re-teaching placement of the replacement end effector in a processing module connected to a wafer handling module mounting the end effectors. Semiconductor processing systems and end effector jigs for replacing end effectors in semiconductor processing systems are also described.

Claims (44)

1. A method replacing an end effector for wafer handling in a semiconductor processing system, comprising:

fixing a first end effector jig to a first stage and a second end effector jig to a second stage of a load lock module;

positioning a first end effector at the first end effector jig and a second end effector at the second end effector jig, the second end effector fixed relative to the first end effector;

fixing the second end effector to the second end effector jig;

replacing the first end effector with a replacement end effector; and

returning the semiconductor processing system to production without re-teaching placement of the replacement end effector in a processing module connected to a wafer handling module mounting the replacement end effector and the second end effector.

2. The method of claim 1 , further comprising acquiring a first end effector position baseline using a fixed sensor while transferring a wafer between the first stage and the first end effector.

3. The method of claim 1 , further comprising acquiring a replacement end effector target position using a carried sensor while transferring a camera wafer between the first stage and the first end effector.

4. The method of claim 1 , further comprising adjusting position of the replacement end effector based on a comparison of position of the replacement end effector with a replacement end effector target position.

5. The method of claim 1 , further comprising verifying position of the replacement end effector based on a comparison of the position of the replacement end effector with a first end effector position baseline.

6. The method of claim 1 , further comprising aligning the replacement end effector with the first end effector jig while the second end effector is fixed to the second stage.

7. The method of claim 1 , wherein the replacement end effector is a first replacement end effector, the method further comprising:

fixing the first replacement end effector to the first end effector jig;

replacing the second end effector with a second replacement end effector; and

returning the semiconductor processing system to production without re-teaching placement of the second replacement end effector in the processing module connected to the load lock module by the back-end wafer handler module.

8. The method of claim 7 , wherein the fixed sensor is a first fixed sensor, the method further comprising acquiring a second end effector position baseline using a second fixed sensor while transferring a wafer between the second stage and the second end effector.

9. The method of claim 7 , further comprising acquiring a second replacement end effector target position using a carried sensor while transferring a camera wafer between the second stage and the second end effector.

10. The method of claim 7 , further comprising adjusting position of the second replacement end effector based on a comparison of position of the second replacement end effector with a second replacement end effector target position.

11. The method of claim 7 , further comprising verifying position of the second replacement end effector based on a comparison of the position of the second replacement end effector with a second end effector position baseline.

12. The method of claim 7 , further comprising aligning the second replacement end effector with the second end effector jig while the first replacement end effector is fixed to the first stage.

13. The method of claim 1 , further comprising:

positioning a transparent cover on the processing module; and

teaching placement of the first end effector in the processing module by observing position of the first end effector in the processing module through the transparent cover.

14. The method of claim 1 , further comprising:

positioning a transparent cover on the processing module; and

teaching placement of the second end effector in the processing module by observing position of the second end effector in the processing module through the transparent cover.

15. A semiconductor processing system, comprising:

a front-end wafer handling module;

a load lock module connected to the front-end wafer handling module, the load lock module having a first stage and a second stage;

a back-end wafer handling module connected to the load lock module, the back-end wafer handling module mounting a first end effector and a second end effector;

a processing module connected to the back-end wafer handling module, the processing module having a first processing stage and a second processing stage;

a first end effector jig fixed to the first stage of the load lock module; and

a second end effector jig fixed to the second stage of the load lock module;

a carried sensor carried by the first end effector and configured to acquire a replacement end effector target position using the carried sensor while transferring a camera wafer between the first stage and the first end effector,

wherein placement of the first end effector in the first processing stage of the processing module corresponds to alignment of the first end effector to the first end effector jig, and

wherein placement of the second end effector in the second processing stage of the processing module corresponds to alignment of the second end effector to the second end effector jig.

16. The semiconductor processing system of claim 15 , wherein the first end effector jig is identical to the second end effector jig.

17. The semiconductor processing system of claim 15 , further comprising a fixed sensor fixed relative to the first stage of the load lock module and configured to acquire a first end effector position baseline using the fixed sensor while transferring a wafer between the first stage and the first end effector.

18. The semiconductor processing system of claim 15 , wherein the first end effector is fixed to the first stage by the first end effector jig.

19. An end effector jig for aligning a replacement end effector to a load lock module in a semiconductor processing system, comprising:

a stage surface with a stage alignment aperture and a stage fixation aperture;

an end effector surface with an end effector alignment aperture, an end effector fixation aperture, and a step;

a stage pin and a stage fastener configured for alignment and fixation of the end effector jig to a stage of the load lock module; and

an end effector pin set configured for alignment and fixation of the replacement end effector to the stage of the load lock module, wherein the step is arranged between stage surface and the end effector surface to allow the replacement end effector to overlay the end effector jig.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 5, 2021
From: CHEN, DONGYANG
To: ASM IP HOLDING B.V.
Reel/Frame 057699/0348 →
Continuity (2)
Provisional Application 63075650 · Sep 8, 2020
Related Publication 20220076986A1 · Mar 10, 2022