Vertical field-effect transistor with wrap-around contact structure
A vertical field-effect transistor device includes a substrate comprising a semiconductor material, and a set of fins formed from the semiconductor material and extending vertically with respect to the substrate. The vertical field-effect transistor device further includes gate structures disposed on the substrate and on a portion of sidewalls of the set of fins, spacers disposed on the gate structures and on a remaining portion of the sidewalls of the set of fins, source/drain regions disposed over top portions of the set of fins, and a metal liner disposed adjacent and over the source/drain regions such that a wrap-around contact is defined to cover an upper area of the source/drain regions. A portion of the source/drain regions is configured to have a lateral width less than a width between adjacent gate structures on the respective fin.
1. A vertical field-effect transistor device, comprising:
a substrate comprising a semiconductor material;
a first fin and a second fin each formed from the semiconductor material and extending vertically with respect to the substrate;
gate structures disposed on the substrate and on a portion of sidewalls of the first fin and the second fin;
spacers disposed on the gate structures and on a remaining portion of the sidewalls of the first fin and the second fin;
a dielectric fill disposed between opposing sidewalls of the spacers and within the gate structures, wherein a top surface of outer ends of the dielectric fill is above a top-most surface of the spacers;
source/drain regions disposed over top portions of the first fin and the second fin; and
a metal liner disposed within the dielectric fill and adjacent and over the source/drain regions such that a wrap-around contact is defined to cover an upper area of the source/drain regions, wherein the wrap-around contact is isolated from the gate structures by the dielectric fill.
2. The vertical field-effect transistor device according to claim 1 , wherein the semiconductor material is silicon.
3. The vertical field-effect transistor device according to claim 1 , further comprising another source/drain region disposed in the substrate and adjacent the first fin and the second fin.
4. The vertical field-effect transistor device according to claim 1 , further comprising a conductive material disposed over the metal liner directly above the source/drain regions disposed over the top portions of the first fin and the second fin.
5. The vertical field-effect transistor device according to claim 1 , wherein the source/drain regions disposed over the top portions of the first fin and the second fin comprise a diamond shaped configuration.
6. The vertical field-effect transistor device according to claim 1 , wherein the gate structures comprise a dielectric layer and a work function metal.
7. The vertical field-effect transistor device according to claim 1 , wherein the first fin and the second fin extend above a top surface of the spacers.
8. The vertical field-effect transistor device according to claim 1 , further comprising an interlevel dielectric layer disposed on opposite sides of the metal liner to define the upper area.
9. An integrated circuit, comprising:
a plurality of semiconductor devices, wherein at least one of the plurality of semiconductor devices comprises a vertical field-effect transistor device comprising:
a substrate comprising a semiconductor material;
a first fin and a second fin each formed from the semiconductor material and extending vertically with respect to the substrate;
gate structures disposed on the substrate and on a portion of sidewalls of the first fin and the second fin;
spacers disposed on the gate structures and on a remaining portion of the sidewalls of the first fin and the second fin;
a dielectric fill disposed between opposing sidewalls of the spacers and within the gate structures, wherein a top surface of outer ends of the dielectric fill is above a top-most surface of the spacers;
source/drain regions disposed over top portions of the first fin and the second fin; and
a metal liner disposed within the dielectric fill and adjacent and over the source/drain regions such that a wrap-around contact is defined to cover an upper area of the source/drain regions, wherein the wrap-around contact is isolated from the gate structures by the dielectric fill.
10. The integrated circuit according to claim 9 , wherein the semiconductor material is silicon.
11. The integrated circuit according to claim 9 , further comprising another source/drain region disposed in the substrate and adjacent the first fin and the second fin.
12. The integrated circuit according to claim 9 , further comprising a conductive material disposed over the metal liner directly above the source/drain regions disposed over the top portions of the first fin and the second fin.
13. The integrated circuit according to claim 9 , wherein the source/drain regions disposed over the top portions of the first fin and the second fin comprise a diamond shaped configuration.
14. The integrated circuit according to claim 9 , wherein the gate structures comprise a dielectric layer and a work function metal.
15. The integrated circuit according to claim 9 , wherein the first fin and the second fin extend above a top surface of the spacers.
16. The integrated circuit according to claim 9 , further comprising an interlevel dielectric layer disposed on opposite sides of the metal liner to define the upper area.
17. A method for fabricating a vertical field-effect transistor device, comprising:
patterning a substrate comprising a semiconductor material;
forming a first fin and a second fin each comprising the semiconductor material and extending vertically with respect to the substrate;
forming gate structures on the substrate and on a portion of sidewalls of the first fin and the second fin;
forming spacers on the gate structures and on a remaining portion of the sidewalls of the first fin and the second fin;
forming a dielectric fill between opposing sidewalls of the spacers and within the gate structures, wherein a top surface of outer ends of the dielectric fill is above a top-most surface of the spacers;
forming source/drain regions over top portions of the first fin and the second fin; and
forming a metal liner within the dielectric fill and adjacent and over the source/drain regions such that a wrap-around contact is defined to cover an upper area of the source/drain regions, wherein the wrap-around contact is isolated from the gate structures by the dielectric fill.
18. The method according to claim 17 , wherein the source/drain regions comprise a diamond shaped configuration.
19. The vertical field-effect transistor device according to claim 1 , wherein the opposing sidewalls are vertical opposing sidewalls.
20. The integrated circuit according to claim 9 , wherein the opposing sidewalls are vertical opposing sidewalls.