Composite substrate for fabricating III-V photodetector arrays

1. A method for forming a composite substrate containing layers of dissimilar materials, the method comprising:

forming a release layer over a base substrate having a buffer layer, the base substrate being composed of a first material;

attaching a metal template layer to the release layer, the metal template layer being composed of a Group III metal;

depositing a capping layer over the metal template layer, the capping layer being composed of a dielectric material;

patterning the metal template layer and the capping layer to form a first composite substrate including a first plurality of separated template units separated by a first plurality of trenches;

annealing the first composite substrate in an ambient gas to form a second composite substrate wherein metal template layer is converted to a first crystalline semiconductor layer which is interposed between the buffer layer and the capping layer; and

removing the capping layer to form a third composite substrate such that the first crystalline semiconductor layer is exposed.

2. The method of claim 1 , wherein the base substrate is a silicon wafer.

3. The method of claim 1 , wherein the ambient gas includes a Group V atom and the first crystalline semiconductor layer is composed of a III-V compound semiconductor.

4. The method of claim 3 , wherein the III-V compound semiconductor is selected from the group consisting of InP, GaAs, InGaAs, AlAs, AlSb, InAs, InN, GaP, GaAs, GaN, AlP, and AlN.

5. The method of claim 3 , wherein the III-V compound semiconductor is grown on the base substrate by templated liquid phase growth.

6. The method of claim 5 , wherein the III-V compound semiconductor is a single crystal.

7. The method of claim 5 , wherein the III-V compound semiconductor is grown in a plurality of regions on the base substrate.

8. The method of claim 7 , wherein the regions all have the same crystal orientation.

9. The method of claim 1 , further comprising selectively growing a second semiconductor layer over the first crystalline semiconductor layer to form a fourth composite substrate.

10. The method of claim 9 , further comprising:

forming a fifth composite substrate by depositing an oxide layer over the second semiconductor layer and which the trenches and then planarization the oxide layer;

forming a sixth composite substrate by selectively removing a portion of oxide layer to form a second set of trenches and growing metal contacts in the second set of trenches; and

forming a seventh composite substrate by singularizing a plurality of compound semiconductor devices wherein the oxide layer, release layer, and buffer layer are etched to a substrate surface of the base substrate.

11. The method of claim 10 , aligning and attaching readout integrated circuits to the seventh composite substrate.

12. The method of claim 9 , wherein at least one compound semiconductor device including the first crystalline semiconductor layer and the second semiconductor layer is formed.

13. The method of claim 12 , wherein a plurality of compound semiconductor devices are formed in different regions on the base substrate.

14. The method of claim 12 , wherein the at least one compound semiconductor device is sensitive to photons.

15. The method of claim 12 , wherein the at least one compound semiconductor device is a photodetector.

16. The method of claim 12 , wherein the compound semiconductor device is a SWIR detector.

17. The method of claim 12 , wherein the compound semiconductor device is designed for LIDAR applications.

18. A composite substrate comprising:

a base substrate;

a buffer layer disposed over the base substrate;

a release layer disposed over the buffer layer;

a first crystalline semiconductor layer disposed over the release layer;

a second semiconductor layer disposed over the first crystalline semiconductor layer; and

an oxide layer is disposed over the first crystalline semiconductor layer and the second semiconductor layer.

19. The composite substrate of claim 18 wherein the base substrate is a silicon wafer.

20. The composite substrate of claim 19 wherein the release layer is composed of a component selected from the group consisting of Mo, NbN, and TiN.

21. The composite substrate of claim 18 , the buffer layer has a thickness from about 100 to 200 nm and the release layer has a thickness from about 10 to 50 nm.

22. The composite substrate of claim 18 , wherein the first crystalline semiconductor layer is composed of InP, GaAs, InGaAs, AlAs, AlSb, InAs, InN, GaP, GaAs, GaN, AlP, or AlN.

23. The composite substrate of claim 18 , wherein the second semiconductor layer is composed of InGaAs.

24. The composite substrate of claim 23 , wherein a compound semiconductor device includes the first crystalline semiconductor layer and the second semiconductor layer.

25. The composite substrate of claim 24 , wherein the compound semiconductor device is a photodetector.

26. The composite substrate of claim 18 further comprising metal contacts embedded in the oxide layer.

27. The composite substrate of claim 26 , wherein an ROIC wafer having metal interconnect pads embedded in oxide is bonded to the composite substrate.

28. The composite substrate of claim 27 , wherein the release layer is configured to be removable to release photodetectors bonded to the ROIC wafer.