Data-weighted element mismatch shaping in digital to analog converters
Embodiments of the disclosure provide improved mismatch shaping for a digital to analog converter, the method including splitting an original input of a circuit into a plurality of time interleaved data streams; element rotation selection (ERS) logic to process the plurality of time interleaved data streams; and directing one of the plurality of time interleaved data streams to the ERS logic according to a decision of a data-weighted sigma-delta (SD) modulator. In other example implementations, the method can further include multiplexing one of the plurality of time interleaved data streams to be provided to a barrel shifter. In yet other examples, the method can include monitoring a difference between the plurality of time interleaved data streams as a basis for the directing such that a data sample rate for the digital to analog converter is reduced over a time interval.
1. A method for mismatch shaping for a digital to analog converter, the method comprising:
splitting an original input of a circuit into a plurality of time interleaved data streams;
directing one of the plurality of time interleaved data streams to element rotation selection (ERS) logic according to a decision of a data-weighted sigma-delta (SD) modulator; and
processing, using the ERS logic, the directed one of the plurality of time interleaved data streams.
2. The method of claim 1 , further comprising:
multiplexing the plurality of time interleaved data streams; and
providing an output of the multiplexing to a barrel shifter.
3. The method of claim 1 , further comprising:
monitoring a difference between the plurality of time interleaved data streams as a basis for the directing such that a data sample rate for the digital to analog converter is reduced over a time interval.
4. The method of claim 1 , further comprising:
disabling a path associated with one of the plurality of time interleaved data streams such that content associated with the path is zeroed out.
5. The method of claim 1 , wherein processing, using the ERS logic, the directed one of the time interleaved data streams includes:
processing, using multiple ERS logic, corresponding directed ones of the plurality of data interleaved streams.
6. The method of claim 1 , further comprising:
driving, using an ERS logic output, a digital-to-analog converter (DAC) unit for analog reconstruction.
7. The method of claim 1 , comprising:
multiplexing the plurality of time interleaved data streams.
8. The method of claim 1 , comprising:
providing an output of a multiplexer to a barrel shifter.
9. An element rotation selection (ERS) system for mismatch shaping, the ERS system comprising:
a first sub-ERS logic;
a second sub-ERS logic;
a first DAC coupled to the first sub-ERS logic;
a second DAC coupled to the second sub-ERS logic, wherein the first and second DACs are to receive an output of the first and second sub-ERS logics to perform a digital to analog conversion; and
a data-weighted sigma-delta (SD) modulator configured to:
monitor a difference between a data weight of the first and second sub-ERS logic; and
select either the first or the second sub-ERS logic to maintain substantially equal usage over time between the first sub-ERS logic and the second sub-ERS logic.
10. The ERS system of claim 9 , wherein the data-weighted SD modulator provides that input weights that move toward two different branches within the ERS system are substantially equal over time.
11. The ERS system of claim 9 , wherein an output at the first and second sub-ERS logic is in a digital form that is being converted into an analog form via the first and second DACs.
12. The ERS system of claim 9 , wherein the first sub-ERS logic and the second sub-ERS logic drive resultants for the first DAC and the second DAC.
13. The ERS system of claim 9 , wherein if one of the first and second sub-ERS logic is not used, its corresponding content is not updated.
14. The ERS system of claim 9 , wherein the first DAC and the second DAC are a same physical DAC.
15. The ERS system of claim 9 , further comprising:
a dither to provide a tone free result for a decision sequence associated with the selection of the first or the second sub-ERS logic.
16. A non-transitory computer readable storage medium storing software code portions configured, when executed on a processor, for mismatch shaping for a digital to analog converter, by:
splitting an original input of a circuit into a plurality of time interleaved data streams;
directing one of the plurality of time interleaved data streams to element rotation selection (ERS) logic according to a decision of a data-weighted sigma-delta (SD) modulator; and
processing, using the ERS logic, the directed one of the plurality of time interleaved data streams.
17. The non-transitory computer readable storage medium according to claim 16 , wherein the software code portions are further configured for:
multiplexing the plurality of time interleaved data streams; and
providing an output of the multiplexing to a barrel shifter.
18. The non-transitory computer readable storage medium according to claim 16 , wherein the ERS logic shares a portion of hardware in which selection code to a barrel shifter is multiplexed, and wherein processing, using the ERS logic, the directed one of the plurality of time interleaved data streams includes:
processing, using multiple ERS logic, corresponding directed ones of the plurality of time interleaved data streams.
19. The non-transitory computer readable storage medium according to claim 16 , wherein the software code portions are further configured for:
monitoring a difference between the plurality of time interleaved data streams as a basis for the directing such that a data sample rate for the digital to analog converter is reduced over a time interval.
20. The non-transitory computer readable storage medium according to claim 16 , wherein the software code portions are further configured for:
providing an output of a multiplexer to a barrel shifter.