Controller to alter systems based on metrics and telemetry
Systems, apparatuses, and methods related to a controller for managing metrics and telemetry are described. A controller includes a front end portion, a central controller portion, a back end portion, and a management unit. The central controller portion can include a cache to store data associated with the performance of the memory operations, metric logic configured to collect metrics related to performance of the memory operations, load telemetry logic configured to collect load telemetry associated with performance of the memory operations within a threshold time, and a storage area to store the collected metrics and the collected load telemetry. The management unit memory of the controller can store metrics and load telemetry associatAND ed with monitoring the characteristics of the memory controller, and based on the stored metrics and load telemetry, alter at least one characteristic of the computing system.
1. An apparatus, comprising:
a memory controller configured to manage a first type of memory device, wherein the memory controller comprises:
a front end portion comprising:
an interface that includes a plurality of input/output (I/O) lanes; and
circuitry to manage the interface;
a central controller portion configured to, in response to receiving a signaling indicative of access requests from a host, perform memory operations, wherein the central controller portion comprises:
a cache to store data associated with the performance of the memory operations;
metric circuitry configured to collect metrics related to performance of the memory operations;
load telemetry circuitry configured to collect load telemetry associated with performance of the memory operations within a threshold time; and
a storage area to store the collected metrics and the collected load telemetry, wherein the collected load telemetry is stored in the storage area after the threshold time;
a back end portion to couple the memory controller to the first type of memory device; and
a management circuitry configured to:
alter at least one timing characteristic of the apparatus, based on the collected metrics and a telemetry ratio obtained from the collected load telemetry, wherein the telemetry ratio is determined by dividing a read telemetry count or a write telemetry count by a preset value, a maximum number of accesses, or a number of accesses over a set time period.
2. The apparatus of claim 1 , wherein the first type of memory device is one of a dynamic random access memory (DRAM) device and a ferroelectric random access memory (FeRAM) device.
3. The apparatus of claim 1 , further comprising a memory controller configured to manage a second type of memory device.
4. The apparatus of claim 1 , wherein the metric circuitry includes a plurality of counters to perform respective counts related to the access requests, and wherein the metrics include information corresponding to the respective counts of the plurality of counters.
5. The apparatus of claim 4 , wherein the plurality of counters comprise at least one of a read hit counter, write hit counter, read miss counter, write miss counter, replacement counter, writeback counter, total read access counter, total write access counter, cache set read access counter, cache set write access counter, or any combination thereof.
6. The apparatus of claim 4 , wherein the cache further comprises a set associative cache, and wherein the metric circuitry is configured to:
collect, via the plurality of counters, a count for each set in the set associative cache; and
determine a most frequently accessed set based on the collected counts.
7. The apparatus of claim 1 , wherein the plurality of I/O lanes are configured to transfer access requests to or from circuitry external to the memory controller according to a compute express link protocol.
8. The apparatus of claim 3 , further comprising a peripheral component interconnect express (PCIe) 5.0 interface coupled to the plurality of I/O lanes, wherein the memory controller is to receive access requests involving at least one of the cache, the first type of memory device, or the second type of memory device, or any combination thereof, via the PCIe 5.0 interface according to a compute express link protocol.
9. The apparatus of claim 1 , wherein the central controller portion further comprises a security circuitry to encrypt data associated with the performance of the memory operations.
10. A system, comprising:
a host; and
a memory controller configured to manage a dynamic random access memory (DRAM) memory device, wherein the memory controller comprises:
a front end portion to couple the memory controller to the host;
a central controller configured to, in response to receiving a signaling indicative of access requests from the host, perform memory operations, wherein the central controller comprises:
a plurality of cache memories including a first cache and a second cache, wherein each cache of the plurality of cache memories comprises:
a metric circuitry including a plurality of counters, the metric circuitry configured to collect, within a threshold amount of time, metrics related to the memory operations using the plurality of counters; and
load telemetry circuitry configured to collect, within the threshold amount of time, load telemetry associated with performing the memory operations using a plurality of load telemetry counters; and
a storage area to store the collected metrics and the collected load telemetry, wherein the collected load telemetry is stored in the storage area after the threshold amount of time;
a back end portion configured to couple the memory controller to the DRAM memory device; and
a management circuitry configured to:
store the collected metrics and the collected load telemetry in the storage area; and
alter at least one of a timing characteristic of an interface in the front end portion, a timing characteristic of the DRAM memory device, a timing characteristic of the cache memories, or any combination thereof, based on the collected metrics and a telemetry ratio obtained from the collected load telemetry, wherein the telemetry ratio is determined by dividing a read telemetry count or a write telemetry count by a preset value, a maximum number of accesses, or a number of accesses over a set time period.
11. The system of claim 10 , wherein the load telemetry circuitry is to calculate a load path of the memory operation using the DRAM memory device.
12. The system of claim 10 , wherein the plurality of counters further comprise:
a memory operation hit counter configured to increase when a memory operation hit is detected; and
a memory operation miss counter configured to increase when a memory operation miss is detected.
13. The system of claim 10 , wherein the management circuitry is further configured to alter a data transfer rate of the interface in the front end portion based on the stored metrics and the collected load telemetry in the storage area.
14. The system of claim 10 , wherein each counter of the plurality of counters is configured to reset to an initial value after the threshold amount of time has elapsed.
15. The system of claim 10 , wherein the storage area further comprises a plurality of rows, each of the plurality of rows includes a plurality of slots, and wherein each counter of the plurality of counters is to store respective counts in a respective row of the plurality of rows.
16. A method, comprising:
receiving a signaling indicative of access requests involving either a first type of memory device or a second type of memory device;
responsive to a receipt of the signaling indicative of the access requests, performing memory operations on a cache of a central controller;
collecting, for a threshold amount of time, information associated with performing the memory operations on the cache, the information including:
metrics collected via a metric circuitry in the central controller; and
load telemetry collected via load telemetry circuitry in the central controller, wherein the collected load telemetry is stored in a storage area after the threshold amount of time; and
altering at least one of a timing characteristic of an interface of a front end, a timing characteristic of a first type of memory device, a timing characteristic of a second type of memory device, a timing characteristic of the cache, or any combination thereof, based on the collected metrics and a telemetry ratio obtained from the collected load telemetry, wherein the telemetry ratio is determined by dividing a read telemetry count or a write telemetry count by a preset value, a maximum number of accesses, or a number of accesses over a set time period.
17. The method of claim 16 , further comprising collecting the information with a plurality of counters.
18. The method of claim 16 , further comprising splitting the cache into at least two sub-cache memories, wherein each sub-cache of the at least two sub-cache memories comprises a respective metric circuitry and a respective load telemetry circuitry.
19. The method of claim 18 , further comprising accessing the sub-cache memories substantially concurrently to collect the information.
20. The method of claim 16 , further comprising receiving the signaling indicative of the access request at a rate of thirty-two gigatransfers per second or greater.