Deep neural network accelerator for optimized data processing, and control method of the deep neural network accelerator

1. A control method of a deep neural network (DNN) accelerator for optimized data processing, the control method comprising:

based on a dataflow and a hardware mapping value of neural network data allocated to a first-level memory, calculating a plurality of offsets representing start components of a plurality of data tiles of the neural network data;

based on receiving an update request for the neural network data from a second-level memory, identifying a data type of an update data tile corresponding to the received update request among the plurality of data tiles;

identifying one or more components of the update data tile, based on the data type of the update data tile and an offset of the update data tile among the calculated plurality of offsets; and

updating neural network data of the identified one or more components between the first-level memory and the second-level memory,

wherein the dataflow comprises information about a data type of the neural network data reused by the second-level memory among the plurality of data types of the neural network data, and

wherein the hardware mapping value comprises information about shapes of data tiles of the neural network data allocated to the first-level memory and the second-level memory.

2. The control method of claim 1 , wherein the calculating of the plurality of offsets comprises, based on a hardware mapping value of each of the plurality of data types, calculating the plurality of offsets for the plurality of data types.

3. The control method of claim 1 , further comprising calculating the required number of updates and the cumulative number of updates of the plurality of data types,

wherein the calculating of the data type of the update data tile comprises identifying the data type of the update data tile, based on the required number of updates and the cumulative number of updates at a time point when the update request is received.

4. The control method of claim 1 , wherein the identifying of the memory address comprises:

calculating a distance to an offset, based on a hardware mapping value of the identified data type; and

identifying a component separated apart from the offset by the distance to the offset as at least one component of the updated data tile.

5. The control method of claim 1 , wherein at least one of the dataflow and the hardware mapping value is determined based on at least one of energy and a data processing cycle that are necessary for an operation of the DNN accelerator.

6. The control method of claim 1 , wherein the second-level memory is a memory at an upper-level than the first-level memory in a memory hierarchy of the DNN accelerator.

7. The control method of claim 6 , wherein the first-level memory comprises a unified buffer that shares regions to which neural network data of the plurality of data types are allocated.

8. The control method of claim 6 , wherein the second-level memory comprises individual buffers having same sizes to which the plurality of data types of the neural network data are allocated, respectively.

9. The control method of claim 1 , wherein, in the DNN accelerator, an interconnection network for transmitting and receiving neural network data does not exist between components respectively including different second-level memories.

10. A deep neural network (DNN) accelerator for optimized data processing, the DNN accelerator comprising:

a first-level memory;

a second-level memory; and

at least one processor configured to control an operation of the first-level memory and an operation of the second-level memory,

wherein the at least one processor is further configured to:

based on a dataflow and a hardware mapping value of the neural network data allocated to the first-level memory, calculate a plurality of offsets representing start components of a plurality of data tiles of the neural network data;

based on receiving an update request for the neural network data from the second-level memory, identify a data type of an update data tile corresponding to the received update request among the plurality of data tiles;

identify a memory address of the first-level memory to which neural network data of the update data tile has been allocated, based on a data type of the update data tile and an offset of the update data tile among the plurality of offsets; and

update neural network data of the identified memory address between the first-level memory and the second-level memory,

wherein the dataflow comprises information about a data type of the neural network data reused by the second-level memory among a plurality of data types of the neural network data, and

wherein the hardware mapping value comprises information about shapes of data tiles of the neural network data allocated to the first-level memory and the second-level memory.

11. The DNN accelerator of claim 10 , wherein the at least one processor is further configured to, based on a hardware mapping value of each of the plurality of data types, calculating a plurality of offsets for the plurality of data types.

12. The DNN accelerator of claim 10 , wherein the at least one processor is further configured to calculate the required number of updates and the cumulative number of updates of the plurality of data types, and identify the data type of the update data tile, based on the required number of updates and the cumulative number of updates at a time point when the update request is received.

13. The DNN accelerator of claim 10 , wherein the at least one processor is further configured to calculate a distance to an offset based on a hardware mapping value of the identified data type, and identify a component spaced apart from the offset by the distance to the offset as at least one component of the update data tile.

14. The DNN accelerator of claim 10 , wherein at least one of the dataflow and the hardware mapping value is determined based on at least one of energy and a data processing cycle that are necessary for an operation of the DNN accelerator.

15. The DNN accelerator of claim 10 , wherein the second-level memory is a memory at an upper-level than the first-level memory in a memory hierarchy of the DNN accelerator.

16. The DNN accelerator of claim 15 , wherein the first-level memory comprises a global buffer composed of a unified buffer that shares regions to which neural network data of the plurality of data types are allocated.

17. The DNN accelerator of claim 15 , wherein the second-level memory comprises individual buffers having same sizes to which the plurality of data types of the neural network data are allocated, respectively.

18. The DNN accelerator of claim 10 , wherein, in the DNN accelerator, an interconnection network for transmitting and receiving neural network data does not exist between components respectively including different second-level memories.

19. A non-transitory computer-readable recording medium having recorded thereon a program, which, when executed by a computer, performs a control method of a deep neural network (DNN) accelerator, the control method comprising:

based on a dataflow and a hardware mapping value of the neural network data allocated to a first-level memory, calculating a plurality of offsets representing start components of a plurality of data tiles of the neural network data;

based on receiving an update request for the neural network data from a second-level memory, identifying a data type of an update data tile corresponding to the received update request among the plurality of data tiles;

identifying one or more components of the update data tile, based on the data type of the update data tile and an offset of the update data tile among the calculated plurality of offsets; and

updating neural network data of the identified one or more components between the first-level memory and the second-level memory,

wherein

the dataflow comprises information about a data type of the neural network data reused by the second-level memory among a plurality of data types of the neural network data, and

the hardware mapping value comprises information about shapes of data tiles of the neural network data allocated to the first-level memory and the second-level memory.