IP Library › Granted Patent US 12,125,876
Granted Patent B2
US 12,125,876 · App. 15/355,783 · Granted Oct 22, 2024

Semiconductor device and method

Inventors: Kuan-Cheng Wang (Toufen Township, TW); Han-Ti Hsiaw (Zhubei, TW)
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
H01L29/0649H01L21/0217H01L21/02321H01L21/31116H01L21/31155H01L21/823431H01L21/823481H01L27/0886H01L29/66545H01L29/66795H01L29/7851H01L21/823878
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Quick Facts
Patent No.
US 12,125,876
App. No.
15/355,783
Granted
Oct 22, 2024
Kind
B2
Abstract

FinFET structures and methods of forming the same are disclosed. In a method, a fin is formed on a substrate, an isolation region is formed on opposing sides of the fin. The isolation region is doped with carbon to form a doped region, and a portion of the isolation region is removed to expose a top portion of the fin, wherein the removed portion of the isolation region includes at least a portion of the doped region.

Claims (23)

1. A method comprising:

forming a fin on a substrate, wherein a top surface of the fin is a first height above the substrate;

forming an isolation region on opposing sidewalls of the fin, wherein the isolation region comprises a dielectric material, wherein a top surface of the isolation region is at least the first height above the substrate;

doping a first portion of the isolation region with carbon to form an upper doped region and a lower doped region, wherein the upper doped region has a concentration of the carbon greater than a concentration of the carbon of the lower doped region, and wherein the upper doped region is farther from the substrate than the lower doped region, and wherein an undoped region of the isolation region is interposed between the substrate and the lower doped region; and

after doping the upper doped region of the isolation region with carbon, removing a second portion of the isolation region to expose a top portion of the fin, wherein the removed second portion of the isolation region comprises at least a portion of the upper doped region.

2. The method of claim 1 , further comprising forming a protective layer over the fin and the substrate before forming the isolation region, wherein the protective layer covers the opposing sidewalls of the fin.

3. The method of claim 1 , wherein forming the isolation region comprises flowing a flowable dielectric material over the substrate.

4. The method of claim 1 , further comprising annealing the isolation region.

5. The method of claim 1 , wherein doping the first portion of the isolation region comprises implanting the carbon within the isolation region.

6. The method of claim 1 , wherein doping the first portion of the isolation region with carbon comprises forming a layer over the isolation region, the layer comprising the carbon, and annealing the layer.

7. The method of claim 1 , wherein removing the second portion of the isolation region comprises an etch process, and wherein a first region of the first portion of the isolation region having a higher concentration of the carbon has an etch rate that is lower than an etch rate of a second region of the first portion of the isolation region having a lower concentration of the carbon.

8. The method of claim 7 , wherein the etch process comprises a plasma etch process.

9. A method comprising:

depositing a dielectric material over a plurality of semiconductor fins, the plurality of semiconductor fins protruding from a substrate, wherein the dielectric material extends along sidewalls of the plurality of semiconductor fins and covers top portions of the plurality of semiconductor fins;

after depositing the dielectric material, adding an impurity into the dielectric material, wherein the impurity extends into the dielectric material from a top surface of the dielectric material to a first depth, wherein the first depth is less than a thickness of the dielectric material, wherein first portions of the dielectric material proximal the top portions of the plurality of semiconductor fins have a first amount of impurity, and wherein second portions of the dielectric material proximal the substrate have a second amount of impurity that is less than the first amount of impurity; and

recessing the first portions of the dielectric material to expose the top portions of the plurality of semiconductor fins.

10. The method of claim 9 , wherein the impurity is carbon.

11. The method of claim 9 , wherein a first region of the dielectric material containing the impurity has a first refractive index and a second region of the dielectric material that is free of the impurity has a second refractive index, wherein the first refractive index is lower than the second refractive index.

12. The method of claim 11 , wherein the first refractive index is in the range from 1.41 to 1.42 and the second refractive index is in the range from 1.43 to 1.46.

13. The method of claim 9 , further comprising forming a buffer layer over the plurality of semiconductor fins and wherein the dielectric material is formed over the buffer layer.

14. The method of claim 13 , wherein the buffer layer comprises silicon nitride.

15. The method of claim 9 , wherein adding the impurity into the dielectric material comprises an implantation process.

16. The method of claim 9 , wherein adjacent semiconductor fins in a first set of the plurality of semiconductor fins are spaced apart a different distance than adjacent semiconductor fins in a second set of the plurality of semiconductor fins.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 27, 2017
From: WANG, KUAN-CHENG; HSIAW, HAN-TI
To: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
Reel/Frame 041108/0367 →
Continuity (1)
Related Publication 20180145131A1 · May 24, 2018
Cited By (1)
US 12,417,945