Resistive random-access memory (ReRAM) cell optimized for reset and set currents
A resistive random-access memory (ReRAM) cell includes a field-effect transistor (FET) and a resistive element. The FET having a gate port, a drain port, and a source port. The gate port is connected to a word-line (WL) of the ReRAM cell, the source port is connected to a bit-line (BL) of the ReRAM cell, and a first port of the resistive element is connected to the drain of the FET. A second port of the resistive element is connected to a source-line (SL) of the ReRAM cell. During reset operation SL is connected to a high-voltage and BL to a low-voltage. During set operation SL is connected to a low-voltage and BL to a high-voltage. Using this common source configuration overcomes the requirement for a wider FET width of the prior art so as to accommodate the current supply needed during reset operation, and avoids overstressing of the FET.
1. A resistive random-access memory (ReRAM) cell comprising:
a bit-line (BL);
a word-line (WL);
a source-line (SL);
a resistive element having a first port and a second port; and
a field-effect transistor (FET) having a gate port, a drain port, and a source port;
wherein the BL is connected to the source port;
wherein the WL is connected to the gate port;
wherein the drain port is connected to the first port of the resistive element;
wherein the SL is connected to the second port of the resistive element; and
wherein the ReRAM cell is adapted to operate in a common source configuration during a reset operation of the resistive element and in a source follower configuration during a set operation of the resistive element.
2. The ReRAM cell of claim 1 , wherein the FET is any one of: an n-type FET (NFET) and a p-type FET (PFET).
3. The ReRAM cell of claim 1 , wherein the FET is any one of: a planar FET, a FinFET, and a metal-oxide semiconductor FETs (MOSFET).
4. The ReRAM cell of claim 1 , wherein, at the reset operation, an absolute voltage at the BL is a low voltage that is lower than an absolute voltage of the SL.
5. The ReRAM cell of claim 4 , wherein the low voltage is 0 V.
6. The ReRAM cell of claim 1 , wherein, at the set operation, an absolute voltage at the SL is a low voltage that is lower than an absolute voltage of the BL.
7. The ReRAM cell of claim 6 , wherein the low voltage is 0 V.
8. The ReRAM cell of claim 1 , wherein the first port of the resistive element is a reactive electrode of a resistor stack.
9. The ReRAM cell of claim 8 , wherein the resistor stack comprises the reactive electrode, an inert electrode, and a resistor body layer deposed therebetween.
10. A resistive random-access memory (ReRAM) comprising:
a ReRAM array, the ReRAM array comprises a plurality of ReRAM cells arranged in rows and columns within the ReRAM array, each ReRAM cell comprises:
a bit-line (BL);
a word-line (WL);
a source-line (SL);
a resistive element having a first port and a second port; and
a field-effect transistor (FET) having a gate port, a drain port, and a source port;
a word-line decoder having a plurality of word-line outputs, wherein each word-line output is connected to a respective word-line input of the ReRAM array;
a bit-line and source-line (BL/SL) decoder having a plurality of bit-line outputs, wherein each bit-line output is connected to a respective bit-line input of the ReRAM array, and wherein the BL/SL decoder having a plurality of source-line outputs, wherein each source-line output is connected to a respective source-line input of the ReRAM array; and
a control logic communicatively connected to the word-line decoder and the BL/SL decoder and adapted to cause the ReRAM cell of the ReRAM array to operate in a common source configuration during reset operation of the resistive element and in a source follower configuration during set operation of the resistive element;
wherein the BL is connected to the source port; wherein the WL is connected to the gate port;
wherein the drain port is connected to the first port of the resistive element;
wherein the SL is connected to the second port of the resistive element;
wherein each row of the ReRAM array has a word-line input connected to the WL of each of the ReRAM cells of a respective row;
wherein each column of the ReRAM array has a bit-line input connected to the BL of each of the ReRAM cells of a respective column; and
wherein each column of the ReRAM array has a source-line input connected to the SL of each of the ReRAM cells of a respective column.
11. The ReRAM of claim 10 , wherein the FET is any one of: an n-type FET (NFET) and a p-type FET (PFET).
12. The ReRAM of claim 10 , wherein the FET is any one of: a planar FET, a FinFET, and a metal-oxide semiconductor FETs (MOSFET).
13. The ReRAM of claim 10 , wherein during the reset operation, an absolute voltage at the BL is a low voltage that is lower than an absolute voltage of the SL.
14. The ReRAM of claim 13 , wherein the low voltage is 0 V.
15. The ReRAM of claim 10 , wherein during the set operation, an absolute voltage at the SL is a low voltage that is lower than an absolute voltage of the BL.
16. The ReRAM of claim 15 , wherein the low voltage is 0 V.
17. The ReRAM of claim 10 , wherein the first port of the resistive element is a reactive electrode of a resistor stack.
18. The ReRAM of claim 17 , wherein the resistor stack comprises the reactive electrode, an inert electrode, and a resistor body layer deposed therebetween.
19. A method for programming a resistive random-access memory (ReRAM) cell, comprising:
applying a lower voltage at a source-line of the ReRAM cell than a voltage at a bit-line of the ReRAM cell for a set operation of a resistive element, wherein the ReRAM cell is adapted to operate in a source follower configuration.
20. The method of claim 19 , further comprising:
determining whether the programming of the ReRAM cell was successful; and
repeating the programming of the ReRAM cell upon determination that the programming was not successful.
21. The method of claim 19 , wherein the ReRAM cell comprises: a bit-line (BL); a word-line (WL); a source-line (SL); a resistive element having a first port and a second port; and a field-effect transistor (FET) having a gate port, a drain port, and a source port; wherein the BL is connected to the source port; wherein the WL is connected to the gate port; wherein the drain port is connected to the first port of the resistive element; and, wherein the SL is connected to the second port of the resistive element.
22. The method of claim 21 , wherein the FET is any one of: an n-type FET (NFET) and a p-type FET (PFET).
23. The method of claim 21 , wherein the first port of the resistive element is a reactive electrode of a resistor stack, wherein the resistor stack comprises the reactive electrode, an inert electrode, and a resistor body layer deposed therebetween.
24. The method of claim 19 , wherein the lower voltage is 0 V.
25. A method for programming a ReRAM cell, comprising:
applying a lower voltage at a bit-line of the ReRAM cell than a voltage at a source-line of the ReRAM cell for a reset operation of a resistive element, wherein the ReRAM cell is adapted to operate in a common source configuration.
26. The method of claim 25 , further comprising:
determining whether the programming of the ReRAM cell was successful; and
repeating the programming of the ReRAM cell upon determination that the programming was not successful.
27. The method of claim 25 , wherein the ReRAM cell comprises: a bit-line (BL); a word-line (WL); a source-line (SL); a resistive element having a first port and a second port; and a field-effect transistor (FET) having a gate port, a drain port, and a source port; wherein the BL is connected to the source port; wherein the WL is connected to the gate port; wherein the drain port is connected to the first port of the resistive element; and, wherein the SL is connected to the second port of the resistive element.
28. The method of claim 27 , wherein the FET is any one of: an n-type FET (NFET) and a p-type FET (PFET).
29. The method of claim 27 , wherein the first port of the resistive element is a reactive electrode of a resistor stack, wherein the resistor stack comprises the reactive electrode, an inert electrode, and a resistor body layer deposed therebetween.
30. The method of claim 25 , wherein the lower voltage is 0 V.