Stacked device with backside power distribution network and method of manufacturing the same
A semiconductor device including a wafer, a first semiconductor device and a second semiconductor device on a front side of the wafer, power rails on a back side of the wafer, a backside power distribution network (PDN) grid on the back side of the wafer, and front-side signal routing lines above the first and second semiconductor devices on the front side of the wafer. The second semiconductor device is stacked on the first semiconductor device, the backside PDN grid is coupled to the power rails, and the power rails are coupled to the first and second semiconductor devices.
1. A CMOS structure comprising:
a wafer;
a first semiconductor device and a second semiconductor device on a front side of the wafer, the second semiconductor device being stacked on the first semiconductor device;
power rails on a back side of the wafer, the power rails being coupled to the first and second semiconductor devices;
a backside power distribution network (PDN) grid on the back side of the wafer, the backside PDN grid being coupled to the power rails; and
front-side signal routing lines on the front side of the wafer, the front-side signal routing lines being coupled to the first and second semiconductor devices and above the first and second semiconductor devices;
a first power via coupled to the power rails and directly coupled to an upper surface of the first semiconductor device;
a second power via coupled to the power rails; and
a power contact coupled to the second power via and to an upper surface of the second semiconductor device,
wherein the first power via comprises a narrower portion below the first semiconductor device and a wider portion above the first semiconductor device,
wherein the first semiconductor device and the second semiconductor device are configured to receive power only from the backside PDN grid.
2. The CMOS structure of claim 1 , wherein the first power via is adjacent to a side of the first semiconductor device.
3. The CMOS structure of claim 1 , wherein the first power via is spaced apart from a side of the first semiconductor device.
4. The CMOS structure of claim 1 , wherein the first semiconductor device is laterally offset from the second semiconductor device.
5. A CMOS structure comprising:
a wafer;
a first semiconductor device and a second semiconductor device on a front side of the wafer, the second semiconductor device being stacked on the first semiconductor device;
power rails on a back side of the wafer, the power rails being coupled to the first and second semiconductor devices;
a backside power distribution network (PDN) grid on the back side of the wafer, the backside PDN being coupled to the power rails;
front-side signal routing lines on the front side of the wafer, the front-side signal routing lines being coupled to the first and second semiconductor devices and above the first and second semiconductor devices;
a first power via coupled to the power rails and directly coupled to an upper surface of the first semiconductor device;
a second power via coupled to the power rails; and
a power contact coupled to the second power via and to an upper surface of the second semiconductor device,
wherein the first power via comprises a narrower portion below the first semiconductor device and a wider portion above the first semiconductor device,
wherein the first semiconductor device is laterally offset from the second semiconductor device, and
wherein the wider portion of the first power via contacts only a portion of the upper surface of the first semiconductor device that is uncovered by the second semiconductor device.
6. The CMOS structure of claim 5 , wherein the first power via contacts a side of the first semiconductor device.
7. The CMOS structure of claim 5 , wherein the wider portion of the first power via extends above the first semiconductor device.