Display panel and display device
View Patent ↗The present application provides a display panel and a display device, the display panel includes a transistor located in a display region, the transistor is at least one of a main transistor, an auxiliary transistor, and a voltage divider transistor. The transistor includes a channel located above a semiconductor layer and a source electrode and a drain electrode located on an electrode layer. The drain electrode includes a drain electrode tip region, and an orthographic projection of the drain electrode tip region on the semiconductor layer is located outside the channel.
1. A display panel, comprising transistors in a display region, the transistors comprising a main transistor, an auxiliary transistor, and a voltage divider transistor, and the transistors comprising a channel located above a semiconductor layer and a source electrode and a drain electrode located on an electrode layer;
wherein the drain electrode comprises a drain electrode tip region, and an orthographic projection of the drain electrode tip region on the semiconductor layer is located outside the channel;
wherein the source electrode comprises a source electrode tip region, and an orthographic projection of the source electrode tip region on the semiconductor layer is located outside the channel;
wherein the transistors comprise the main transistor, the main transistor comprises a first channel located in the semiconductor layer and a first source electrode and a first drain electrode located on the electrode layer;
wherein the first drain electrode comprises a first drain electrode tip region, and an orthographic projection of the first drain electrode tip region on the semiconductor layer is located outside the first channel;
wherein the first source electrode comprises a first source electrode tip region, and an orthographic projection of the first source electrode tip region on the semiconductor layer is located outside the first channel;
wherein the first channel comprises a first aperture, and the orthographic projection of the first drain electrode tip region on the semiconductor layer is located in the first aperture.
2. The display panel according to claim 1 , wherein the first channel comprises a second aperture, and the orthographic projection of the first source electrode tip region on the semiconductor layer is located in the second aperture.
3. The display panel according to claim 2 , wherein the first aperture is a concave aperture, or is a fully closed or semi-closed aperture; and
the second aperture is a concave aperture or, is a fully closed or semi-closed aperture.
4. The display panel according to claim 1 , wherein the auxiliary transistor comprises a second channel located in the semiconductor layer and a second source electrode and a second drain electrode located on the electrode layer; and
the second drain electrode comprises a second drain electrode tip region, and an orthographic projection of the second drain electrode tip region on the semiconductor layer is located outside the second channel.
5. The display panel according to claim 4 , wherein the second source electrode comprises a second source electrode tip region, and an orthographic projection of the second source electrode tip region on the semiconductor layer is located outside the second channel.
6. The display panel according to claim 5 , wherein the second channel comprises a third aperture, the orthographic projection of the second drain electrode tip region on the semiconductor layer is located in the third aperture.
7. The display panel according to claim 6 , wherein the second channel comprises a fourth aperture, and the orthographic projection of the second source electrode tip region on the semiconductor layer is located in the fourth aperture.
8. The display panel according to claim 7 , wherein the third aperture is a concave aperture, or is a fully closed or semi-closed aperture; and
the fourth aperture is a concave aperture, or is a fully closed or semi-closed aperture.
9. The display panel according to claim 1 , wherein the voltage divider transistor comprises a third channel located in the semiconductor layer and a third source electrode and a third drain electrode located on the electrode layer; and
the third drain electrode comprises a third drain electrode tip region, and an orthographic projection of the third drain electrode tip region on the semiconductor layer is located outside the third channel.
10. The display panel according to claim 9 , wherein the third source electrode comprises a third source electrode tip region, and an orthographic projection of the third source electrode tip region on the semiconductor layer is located outside the third channel.
11. The display panel according to claim 10 , wherein the third channel comprises a fifth aperture, and an orthographic projection of the third drain electrode tip region on the semiconductor layer is located in the fifth aperture.
12. The display panel according to claim 11 , wherein the third channel comprises a sixth aperture, and an orthographic projection of the third source electrode tip region on the semiconductor layer is located in the sixth aperture.
13. The display panel according to claim 12 , wherein the fifth aperture is a concave aperture, or is a fully closed or semi-closed aperture; and
the sixth aperture is a concave aperture, or is a fully closed or semi-closed aperture.
14. The display panel according to claim 9 , wherein the display panel further comprises a main pixel electrode and an auxiliary pixel electrode, the main transistor is electrically connected to the main pixel electrode, and the auxiliary transistor and the voltage divider transistor are electrically connected to the auxiliary pixel electrode.
15. A display device, comprising the display panel according to claim 1 .
16. A display panel, comprising a main transistor, an auxiliary transistor, and a voltage divider transistor;
wherein the main transistor comprises a first channel located in a semiconductor layer and a first source electrode and a first drain electrode located on an electrode layer, the first drain electrode comprises a first drain electrode tip region, an orthographic projection of the first drain electrode tip region on the semiconductor layer is located outside the first channel, the first source electrode comprises a first source electrode tip region, and an orthographic projection of the first source electrode tip region on the semiconductor layer is located outside the first channel;
wherein the auxiliary transistor comprises a second channel located in the semiconductor layer and a second source electrode and a second drain electrode located on the electrode layer, the second drain electrode comprises a second drain electrode tip region, an orthographic projection of the second drain electrode tip region on the semiconductor layer is located outside the second channel, the second source electrode comprises a second source electrode tip region, and an orthographic projection of the second source electrode tip region on the semiconductor layer is located outside the second channel; and
wherein the voltage divider transistor comprises a third channel located in the semiconductor layer and a third source electrode and a third drain electrode located on the electrode layer, the third drain electrode comprises a third drain electrode tip region, an orthographic projection of the third drain electrode tip region on the semiconductor layer is located outside the third channel, the third source electrode comprises a third source electrode tip region, and an orthographic projection of the third source electrode tip region on the semiconductor layer is located outside the third channel.