IP Library › Granted Patent US 12,136,391
Granted Patent B2
US 12,136,391 · App. 17/982,931 · Granted Nov 5, 2024

Pixel circuit

Inventor: Keunwoo Kim (Seongnam-si, KR)
Assignee: SAMSUNG DISPLAY CO., LTD.
G09G3/3233G09G3/30G09G3/32G09G3/3258G09G2300/0819G09G2300/0842G09G2300/0852G09G2310/0251G09G2320/0247
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Quick Facts
Patent No.
US 12,136,391
App. No.
17/982,931
Granted
Nov 5, 2024
Kind
B2
Abstract

A pixel circuit includes a light emitting element, a driving transistor which applies a driving current to the light emitting element, a write transistor which receives a write gate signal and a data voltage and is connected to a first electrode of the driving transistor, a first compensation transistor which receives a compensation gate signal and is connected to a second electrode of the driving transistor and a first electrode of a second compensation transistor, the second compensation transistor which receives the compensation gate signal, and is connected to the second electrode of the first compensation transistor and a control electrode of the driving transistor, a storage capacitor which receives a first power voltage and is connected to the control electrode of the driving transistor, and a node control transistor which receives the write gate signal and is connected to the second electrode of the first compensation transistor.

Claims (23)

1. A pixel circuit comprising:

a light emitting element;

a driving transistor which applies a driving current to the light emitting element;

a write transistor including a control electrode which receives a write gate signal, a first electrode connected to a first electrode of the driving transistor, and a second electrode which receives a data voltage;

a first compensation transistor including a control electrode which receives a compensation gate signal, a first electrode connected to a second electrode of the driving transistor, and a second electrode connected to a first electrode of a second compensation transistor;

the second compensation transistor including a control electrode which receives the compensation gate signal, the first electrode connected to the second electrode of the first compensation transistor, and a second electrode connected to a control electrode of the driving transistor;

a storage capacitor including a first electrode which receives a first power voltage and a second electrode connected to the control electrode of the driving transistor; and

a node control transistor including a control electrode which receive the write gate signal, a first electrode directly connected to only the second electrode of the first compensation transistor and the first electrode of the second compensation transistor, and a second electrode.

2. The pixel circuit of claim 1 , wherein a first initialization voltage is applied to the second electrode of the node control transistor.

3. The pixel circuit of claim 1 , further comprising:

a gate initialization transistor including a control electrode which receives an initialization gate signal, a first electrode connected to the control electrode of the driving transistor, and a second electrode which receives a second initialization voltage, and

wherein the second electrode of the node control transistor is connected to the first electrode of the gate initialization transistor.

4. The pixel circuit of claim 3 , wherein the write transistor, the first compensation transistor, and the second compensation transistor are turned on from an off-state to an on-state when the gate initialization transistor is in the on-state in a non-emission period in which a gate initialization operation and a data writing operation are performed.

5. The pixel circuit of claim 1 , wherein the node control transistor, the first compensation transistor, and the second compensation transistor are in an on-state in a first data writing period of a non-emission period in which a gate initialization operation and a data writing operation are performed, and

wherein the node control transistor is in an off-state and the first compensation transistor and the second compensation transistor are in the on-state in a second data writing period of the non-emission period after the first data writing period.

6. The pixel circuit of claim 1 , further comprising:

an anode initialization transistor including a control electrode which receives a bias signal, a first electrode connected to an anode electrode of the light emitting element, and a second electrode which receives a first initialization voltage;

a gate initialization transistor including a control electrode which receives an initialization gate signal, a first electrode connected to the control electrode of the driving transistor, and a second electrode which receives a second initialization voltage;

a first emission transistor including a control electrode which receives an emission signal, a first electrode which receives the first power voltage, and a second electrode connected to the first electrode of the driving transistor;

a second emission transistor including a control electrode which receives the emission signal, a first electrode connected to the second electrode of the driving transistor, and a second electrode connected to the anode electrode of the light emitting element; and

a bias transistor including a control electrode which receives the bias signal, a first electrode which receives a bias voltage, and a second electrode connected to the first electrode of the driving transistor.

7. The pixel circuit of claim 6 , wherein the gate initialization transistor is configured as a dual.

8. The pixel circuit of claim 6 , wherein a frequency of the bias signal is greater than a frequency of the write gate signal.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 23, 2023
From: KIM, KEUNWOO
To: SAMSUNG DISPLAY CO., LTD.
Reel/Frame 063723/0729 →
Priority Claims (1)
KR 10-2022-0013233 · Jan 28, 2022 · national
Continuity (1)
Related Publication 20230245616A1 · Aug 3, 2023