Method of fabricating a semiconductor device
A semiconductor device and a semiconductor package, the device including a first buffer dielectric layer on a first dielectric layer; a second dielectric layer and a second buffer dielectric layer sequentially disposed on the first buffer dielectric layer, the second buffer dielectric layer being in contact with the first buffer dielectric layer; and a pad interconnection structure that penetrates the first buffer dielectric layer and the second buffer dielectric layer, wherein the pad interconnection structure includes copper and tin.
1. A method of fabricating a semiconductor device, the method comprising:
preparing a first pad structure including a first pad and a first bonding metal pad on the first pad;
preparing a second pad structure including a second pad and a second bonding metal pad on the second pad;
stacking the second pad structure on the first pad structure so that the first bonding metal pad and the second bonding metal pad face each other; and
forming a pad interconnection structure connecting the first pad and the second pad from the first bonding metal pad and the second bonding metal pad,
wherein:
the pad interconnection structure includes:
a central part,
a first intermediate part surrounding the central part,
a second intermediate part surrounding the first intermediate part, and
an outer part surrounding the second intermediate part,
a grain size of the outer part is less than a grain size of the second intermediate part,
the grain size of the second intermediate part is less than a grain size of the first intermediate part, and
the grain size of the first intermediate part is less than a grain size of the central part.
2. The method of fabricating a semiconductor device as claimed in claim 1 , wherein the first bonding metal pad includes copper and tin.
3. The method of fabricating a semiconductor device as claimed in claim 1 , wherein forming the pad interconnection structure comprises performing an annealing process to combine the first bonding metal pad and the second bonding metal pad.
4. The method of fabricating a semiconductor device as claimed in claim 3 , wherein the annealing process is performed at 250° C. to 350° C.
5. The method of fabricating a semiconductor device as claimed in claim 1 , wherein preparing the first pad structure comprises:
forming a first buffer dielectric layer, an insulating layer, and a second buffer dielectric layer on the first pad;
forming a trench penetrating the first buffer dielectric layer, the insulating layer, and the second buffer dielectric layer to expose a top surface of the first pad; and
forming the first bonding metal pad in the trench.
6. The method of fabricating a semiconductor device as claimed in claim 5 , wherein preparing the first pad structure further comprises forming a connection barrier layer between the first bonding metal pad and the first pad.
7. The method of fabricating a semiconductor device as claimed in claim 1 , wherein the first bonding metal pad has a convexly curved surface in a direction away from the first pad.
8. The method of fabricating a semiconductor device as claimed in claim 1 , further comprising performing an annealing process to reduce a volume of the pad interconnection structure.
9. The method of fabricating a semiconductor device as claimed in claim 1 , wherein the pad interconnection structure includes copper and tin.
10. The method of fabricating a semiconductor device as claimed in claim 9 , wherein:
an amount of tin contained in the pad interconnection structure decreases in a direction toward the central part of the pad interconnection structure from the outer part of the pad interconnection structure, and
an amount of copper contained in the pad interconnection structure increases in the direction toward the central part from the outer part.
11. A method of fabricating a semiconductor device, the method comprising:
preparing a first pad structure including a first pad, a first buffer dielectric layer on the first pad, and a first bonding metal pad passing through the first buffer dielectric layer and connected to the first pad;
preparing a second pad structure including a second pad, a second buffer dielectric layer on the second pad, and a second bonding metal pad passing through the second buffer dielectric layer and connected to the second pad;
contacting the first bonding metal pad and the second bonding metal pad to form a gap between the first buffer dielectric layer and the second buffer dielectric layer; and
forming a pad interconnection structure from the first bonding metal pad and the second bonding metal pad,
wherein:
the pad interconnection structure includes copper and tin, and
forming the pad interconnection structure includes performing an annealing process to remove the gap, thereby the first buffer dielectric layer contacting the second buffer dielectric layer.
12. The method of fabricating a semiconductor device as claimed in claim 11 , wherein a volume of the pad interconnection structure is reduced while the annealing process is performed.
13. The method of fabricating a semiconductor device as claimed in claim 11 , wherein the pad interconnection structure comprises an intermetallic compound.
14. The method of fabricating a semiconductor device as claimed in claim 11 , wherein the first bonding metal pad has a convexly curved surface in a direction away from the first pad.
15. The method of fabricating a semiconductor device as claimed in claim 11 , wherein:
the pad interconnection structure includes:
a central part,
a first intermediate part surrounding the central part,
a second intermediate part surrounding the first intermediate part, and
an outer part surrounding the second intermediate part,
a grain size of the outer part is less than a grain size of the second intermediate part,
the grain size of the second intermediate part is less than a grain size of the first intermediate part, and
the grain size of the first intermediate part is less than a grain size of the central part.
16. The method of fabricating a semiconductor device as claimed in claim 15 , wherein:
an amount of tin contained in the pad interconnection structure decreases in a direction toward the central part of the pad interconnection structure from the outer part of the pad interconnection structure, and
an amount of copper contained in the pad interconnection structure increases in the direction toward the central part from the outer part.